Polarity reversal tolerant electrical circuit for ESD...

Details Polarity reversal tolerant electrical circuit for ESD... Polarity reversal tolerant electrical circuit for ESD...

2001-12-18

2003-12-02

Sherry, Michael (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S082000, C361S084000, C361S111000, C307S127000

Reexamination Certificate

active

06657836

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to over voltage protection of electrical circuits and more specifically to the area of protecting electrical circuits from an electrostatic discharge (ESD) over voltage while tolerating a reverse polarity condition applied to the electrical circuit input terminals.
BACKGROUND OF THE INVENTION
A common cause of failure in electronic integrated circuits (ICs) is due to a sudden exposure to a large over voltage condition known as electrostatic discharge (ESD). In manufacturing the ICs or while using these ICs to assemble a product they are susceptible to ESD. Electrostatic charge build up typically results from contact and later removal of dissimilar materials from one another and ESD results from the flow of this charge.
When a charged item comes in contact with an IC, especially when a portion of the IC is grounded, the electrical charge very quickly discharges by traveling through the IC to ground. ESD voltages during an ESD discharge event range as high as 2 KVolts, jumping air gaps of over a mm in length. In current CMOS technology, gaps between conductors and various components within the IC are in the order of sub microns. The advantages seen by improving performance characteristics of ICs, such as speed and lower operating voltages, are offset by increased sensitivity to ESD. These smaller and more efficient chip sizes, have much smaller electrical bus conductors and as a result can be easily damaged. In these ICs MOS transistor gate oxides are more fragile and have much lower breakdown voltages. Prior to sub micron technology utilized for manufacturing of ICs the larger chips had more capacitance with more area for charge storage, and as a result were not as susceptible to ESD related damage; having smaller IC features results in a higher potential for ESD related problems.
These smaller conductors and components within the ICs have a very limited current carrying capacity, and often times the ESD result in the conductors and components acting like fuses, thereby blowing, or shorting, or melting the conductors and components within the integrated circuit, rendering the electrical circuit damaged and more likely useless. Components manufactured from oxides and other films within MOS devices are unlikely to withstand high dielectric breakdown conditions since a high level of current flows through very small cross sectional areas of the circuit. This resistive heating in elements like diodes, transistors and resistors melts conductive material such as polysilicon or aluminum. This molten material within the circuit flows along the electric field lines creating short circuits within the IC. ESD for instance causes short circuits between source and drain in MOSFET devices, or reverse breakdown of p-n junctions in transistors or diodes. In most cases these short circuits remain after the ESD event has completed and likely renders the electrical circuit useless for its designated purpose.
Generally, MOS type integrated circuits are prone to ESD damage if their input and output pins are left unprotected, especially during handling of the integrated circuit. As a result a common IC design industry practice is to place some form of ESD protection within the IC such that these deleterious currents do not flow through sensitive paths. Typically the built-in ESD protection devices take the form of additional circuits placed between the input pins, output pins and supply voltage rails.
Common methods of providing ESD protection to ICs include using diodes, such as Zener diodes for CMOS circuits. The applied ESD energy then dissipates through the diode by avalanche breakdown or punch through creating a low resistance path to ground, channeling the deleterious electrical potential to ground, thereby offering protection to the IC.
In U.S. Pat. No. 5,416,351 to Ito et al. is disclosed an ESD protection circuit to coupled NMOS and PMOS devices by using a Zener region formed in the drain to assist in NMOS and PMOS diode breakdown, and in U.S. Pat. No. 5,528,064 to Thiel et al is disclosed ESD protection for MOS devices by using back-to-back Zener diodes. Using back-to-back diodes provide some ESD protection but unfortunately allows too much voltage to pass within new generation MOS devices that are made with thinner gate oxides in sub micron CMOS devices.
An alternate technique for ESD protection is disclosed in U.S. Pat. No. 6,233,130 by Lin. This technique utilizes a transient high-voltage pumping circuit for pumping the ESD voltage to a higher voltage during an ESD event for early triggering of the SCR (silicon-controlled rectifiers) during an ESD event. SCRs provide adequate protection but are not desirable on power busses due to their tendency to latchup. Latchup occurs when the input signals are outside a predefined voltage range. When latchup occurs, a channel substrate diode within the SCR become conducting and floods the substrate with charge carriers.
In U.S. Pat. No. 5,959,820, Ker, et al. disclose removal of the latchup condition by providing a holding voltage on the low voltage trigger SCR (LVTSCR) which is greater than the supply voltage on the IC. Increasing the holding voltage on the LVTSCR is accomplished by providing double guard rings surrounding both the anode and the cathode of a LVTSCR device. The guarding structure breaks the latching path and increases the holding voltage of the LVTSCR. However increasing the holding voltage of an LVTSCR leads to more power dissipation at the LVTSCR during an ESD transition and using a double guard rings results in a lower ESD robustness of the LVTSCR. Furthermore guard rings occupy more layout spacing on the IC die and are therefore costly.
It is therefore an object of the present invention to provide an ESD protection circuit which provides substantial protection for sub micron CMOS technology integrated circuits.
It is another the object of the present invention to provide ESD protection without latchup problems in the ESD protection circuit, while offering bipolar ESD protection circuit operation.
SUMMARY OF THE INVENTION
In accordance with the invention there is provided an ESD protection circuit comprising:
a first voltage input port;
a second voltage input port;
an ESD protection circuit including a primary transistor comprising a first port a second port and a control port for controlling current flow between the first port and the second port, the first port and the second port coupled electrically between the first voltage input port and the second voltage input port; and,
a polarity independent control circuit for providing a same voltage at the control port of the primary transistor within the ESD protection circuit regardless of the polarity of the voltage applied across the first voltage input port and the second voltage input port.
In accordance with another aspect of the invention there is provided an ESD protection circuit comprising:
a first voltage input port;
a second voltage input port;
a common bulk node;
a primary ESD protection transistor having a first port coupled to the second voltage input port, a second port coupled to the second voltage input port, and a control port coupled to the common bulk node for controlling current flow between the first port and the second port;
a secondary ESD protection transistor having a first port electrically coupled to the second voltage input port, a second port coupled to the first voltage input port, and a control port coupled to the common bulk node for controlling current flow between the first port and the second port;
a forward bias transistor having a first port electrically coupled to the second voltage input port, a second port coupled to the common bulk, and a control port electrically coupled to the first voltage input port for controlling current flow between the first port and the second port; and
a reverse bias transistor having a first port coupled to the common bulk node a second port coupled to the first voltage input port and a control port electrically coupled to the first port of the forward bias transisto

Affiliated with

Also associated with

Rating

Polarity reversal tolerant electrical circuit for ESD... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Polarity reversal tolerant electrical circuit for ESD..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Polarity reversal tolerant electrical circuit for ESD... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3174018