Polarity option control logic for use with a register of a progr

Details Polarity option control logic for use with a register of a progr Polarity option control logic for use with a register of a progr

1988-12-16

1990-04-03

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307236, 307469, 307481, H03K 19177

Patent

active

049143220

ABSTRACT:
Polarity option control logic is disclosed which provides an optimized design for a macrocell of a programmable logic array with a minimal parts count.
The invention is designed for use with a register of the macrocell having first and second input paths, the first input path including an inverter, and first and second switches in each path respectively. The polarity option control logic of the present invention includes a first logic circuit for receiving a clock input and a polarity input signal and controlling the activation of the first switch in response thereto and a second logic circuit for receiving the clock input and an inverted polarity input signal and controlling the activation of the second switch in response thereto. When the polarity input signal is in a first state, the first input path is enabled via the first switch in accordance with the clock signal and when the polarity input signal is in a second state, the second input path is enabled via the second switch in accordance with the clock signal.
In a particular embodiment, a macrocell is provided including polarity option control logic, a bypass option, a high speed multiplexer and an advantageous preload circuit that minimizes parasitic capacitances at the register input. Thus, a macrocell constructed in accordance with the present teachings, can be configured in a register mode with set, reset and preload features or a logic mode with an optimized speed path for both modes of operation.

REFERENCES:
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patent: 4783606 (1988-11-01), Goetting
patent: 4789951 (1988-12-01), Birkner et al.
Barish et al., "Polarity Hold Latch in a Shift Register Latch to Decrease the Minimum Pulse Width for Test Cycle Time", IBM T.D.B., vol. 20, No. 3, Aug. 1977, pp. 1025-1026.

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