Pointer processing and path BIP-8 computation for large...

Details Pointer processing and path BIP-8 computation for large... Pointer processing and path BIP-8 computation for large...

2006-05-16

2006-05-16

Lee, Andy (Department: 2663)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S535000

Reexamination Certificate

active

07046699

ABSTRACT:
A system for performing Bit Interleaved Parity-8 (BIP-8) computation on large concatenated payloads, in a processing node of an optical communications networks. The BIP-8 computation system comprises storage means associated with each processing strip for allowing the comparison between calculated and transmitted frame error check values to be delayed.

REFERENCES:
patent: 5113395 (1992-05-01), Murakami et al.
patent: 5142529 (1992-08-01), Parruck et al.
patent: 5172376 (1992-12-01), Chopping et al.
patent: 5331630 (1994-07-01), Fujita et al.
patent: 5461622 (1995-10-01), Bleickardt et al.
patent: 5471476 (1995-11-01), Hiramoto
patent: 5535219 (1996-07-01), Freitas
patent: 5696788 (1997-12-01), Choi et al.
patent: 5751720 (1998-05-01), Uematsu et al.
patent: 5796796 (1998-08-01), Wang
patent: 5809032 (1998-09-01), Weeber et al.
patent: 6339628 (2002-01-01), Yoshida
patent: 6400785 (2002-06-01), Sunaga et al.

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