Pointer generator design that provides multiple outputs that...

Details Pointer generator design that provides multiple outputs that... Pointer generator design that provides multiple outputs that...

2005-05-03

2005-05-03

Chin, Wellington (Department: 2664)

Multiplex communications

Pathfinding or routing

Through a circuit switch

C370S907000

Reexamination Certificate

active

06888826

ABSTRACT:
A SONET multiplexed communications system that facilitates the sharing of processing resources while reducing overall system complexity. The SONET multiplexed communications system includes a single multi-output pointer generator clocked by a system clock and a plurality of clock domain transfer circuits having respective FIFO buffers for transferring SONET signals from the system clock domain to respective outgoing line clock domains. The multi-output pointer generator and the clock domain transfer circuits compensate for timing differences between the system clock and the respective outgoing line clocks by either skipping or overwriting FIFO buffer address locations corresponding to TOH byte positions in outgoing SONET frames. The TOH bytes corresponding to the skipped or overwritten TOH byte positions are subsequently re-generated by respective TOH insertion circuits before the outgoing SONET frames are passed through outgoing SONET lines.

REFERENCES:
patent: 5241543 (1993-08-01), Amada et al.
patent: 5245636 (1993-09-01), Sari et al.
patent: 5430659 (1995-07-01), Miller
patent: 5535219 (1996-07-01), Freitas
patent: 5563890 (1996-10-01), Freitas
patent: 5699391 (1997-12-01), Mazzurco et al.
patent: 5717693 (1998-02-01), Baydar et al.
patent: 5790557 (1998-08-01), Lee et al.
patent: 5835543 (1998-11-01), Mazzurco et al.
patent: 6208666 (2001-03-01), Lawrence et al.
patent: 6377640 (2002-04-01), Trans
patent: 6775799 (2004-08-01), Giorgetta et al.
patent: 6782009 (2004-08-01), Giorgetta et al.
patent: 6795451 (2004-09-01), Giorgetta et al.
patent: 6823137 (2004-11-01), Fujita
patent: 20010003484 (2001-06-01), Fujita
patent: 20010038674 (2001-11-01), Trans
patent: 20020110157 (2002-08-01), Jorgenson et al.
patent: 20020172227 (2002-11-01), Varelas et al.

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