1985-09-18
1987-03-10
Clawson, Jr., Joseph E.
357 38, 357 35, 357 43, 357 51, 357 59, H01L 2940
Patent
active
046494146
ABSTRACT:
In a planer type PNPN semiconductor switch having a MOS FET structure, a field plate electrode is embedded in an insulator covering a surface of a semiconductor substrate to overlie an interface between the semiconductor substrate and a P gate region for limiting an extention of a depletion layer from an anode region to a P gate region.
REFERENCES:
patent: 3432731 (1969-03-01), Whittier
patent: 3858235 (1974-12-01), Schild
patent: 4244000 (1981-01-01), Ueda et al.
patent: 4414560 (1983-11-01), Lidow
F. Perner et al., "MOS Gate Turn-Off Cateral Scr," IBM Tech. Discl. Bull., vol. 20, #6, Nov. 1977, pp. 2273, 2274.
J. Ueda et al., "An Opt. - Coupl. . . . Sensitivity," IEEE Journal of Solid-State Circuits, vol. SC-16, No. 4, Aug. 1981, pp. 286-293.
Nanba Yoichi
Tsukada Hirokazu
Ueda Jun
Clawson Jr. Joseph E.
OKI Electric Industry Co., Ltd.
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