PNP-type lateral transistor with minimal substrate operation int

Details PNP-type lateral transistor with minimal substrate operation int PNP-type lateral transistor with minimal substrate operation int

1983-12-05

1986-04-08

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576W, 29578, 29579, 148 15, 148187, 357 35, 357 50, 156643, 156648, H01L 2122, H01L 2176

Patent

active

045803315

ABSTRACT:
The invention provides a unique VLSI dimensioned PNP-type transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Slots made in the substrate permit angle evaporation of etch-resist to protect the active region while it is disconnected from the substrate by etching therebeneath via the slots. Substrate oxidation supports the active regions while orthogonal slots are provided permitting access to opposed sides of the active regions for doping N+ which is driven in from one side only while P or P+ is introduced and driven in from both sides, thereby providing a P+ N+N, P+ emitter, base, collector transistor active region to which electrical connections are applied using conventional techniques, providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

REFERENCES:
patent: 4437226 (1984-03-01), Soclof
patent: 4466180 (1984-08-01), Soclof

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