PNP high-current, high-swing output stage and method

Details PNP high-current, high-swing output stage and method PNP high-current, high-swing output stage and method

2000-04-06

2002-04-02

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including push-pull amplifier

C330S292000, C330S296000

Reexamination Certificate

active

06366170

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to amplifier circuits and, in particular, an output stage of an amplifier capable of providing high currents at output levels close to the power supply rail.
2. Description of Related Art
There is an increasing demand for amplifier circuits having the capability of accepting input signals that come very close to the upper and lower supply voltages and capable of providing outputs which have the same capability. This is especially true in those application where the power supply voltages are small.
FIG. 1A
is a schematic diagram of part of a conventional amplifier output. A PNP output transistor QA has an emitter coupled to the positive supply voltage VCC and a collector coupled to the amplifier output. Thus, transistor QA is capable of sourcing current to a load. Although not shown, there is typically another device connected to the output for sinking current from a load.
PNP transistor QA is driven by a pair of Darlington-connected NPN transistors QB and QC. A resistor RA is connected between the base and emitter of transistor QA. When driven hard, transistor QA is capable of becoming saturated so that the output can be pulled up within one saturation voltage of the positive supply VCC. Since the saturation voltage is typically on the order of tenths of a volt, the
FIG. 1A
circuit is capable of providing a high voltage swing, a very desirable feature in many applications.
The
FIG. 1A
circuit does posses certain shortcomings. By way of example, the settling time of the circuit is poor due to the high overall transconductance (gm) of the circuit. Further, the gam of the circuit changes significantly with changes in output current thereby making the circuit difficult to stabilize.
FIG. 2A
is a schematic diagram of a portion of an alternative prior art output stage. Again, the output stage utilizes a PNP transistor QD having an emitter coupled to the positive supply VCC and a collector coupled to the output. Thus, the output is capable of swing up to almost the positive power supply VCC level. Transistor QD is driven by a pair of Darlington-connected NPN transistors QG and QF. A second PNP transistor QE is connected as a diode, with the base and emitter of QE being connected to the base and emitter of transistor QD, respectively.
The
FIG. 1B
circuit is an improvement over the
FIG. 1A
circuit in that the current gain is reduced by the presence of QE. Transistors QD and QE form a current mirror circuit, with the ratio of the currents limiting the current gain to a value substantially less than the current gain of transistor QD alone. The current ratio is determined by the ratio of the emitter areas of QE and QB, with QD typically being ten times as large as that of QB. Further, the slew rate or settling time of the circuit is improved over that of the
FIG. 1A
circuit.
Capacitor CA provides of Miller capacitor feedback which operates to stabilize the circuit. However, the impedance is so low at the base of transistor QE, the Miller capacitor feedback is not very effective. This makes the
FIG. 1B
circuit difficult to stabilize, particularly for large capacitive loads.
There is a need for an amplifier output stage capable of providing a high voltage swing and yet can be easily stabilized for a wide range of load currents and load capacitance. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings, the present invention provides these and other advantages.
SUMMARY OF THE INVENTION
An amplifier output stage of an amplifier, including a PNP transistor having a collector coupled to an amplifier output and an emitter coupled to a first power supply rail. A second transistor, an NPN transistor, is included having a base for receiving an input signal and a collector coupled to the base of the first PNP transistor. The output stage includes a frequency compensation capacitor having one terminal coupled the PNP transistor. A bias circuit is included which produces a bias voltage across the base-emitter junction of the PNP transistor. The bias voltage is independent of current flow through the PNP transistor and causes the PNP transistor to conduct a desired quiescent current. The bias circuit has an effective output impedance sufficiently large to form a pole in combination with the frequency compensation capacitor at a frequency beyond the unity-gain frequency of the amplifier.


REFERENCES:
patent: 4366447 (1982-12-01), Sugiyama
patent: 5081426 (1992-01-01), Imanishi
patent: 5337012 (1994-08-01), Dijkmans
patent: 5825247 (1998-10-01), Herrlinger
patent: 6011431 (2000-01-01), Gilbert

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