PMOS wordline boost cricuit for DRAM

Details PMOS wordline boost cricuit for DRAM PMOS wordline boost cricuit for DRAM

1991-01-02

1991-12-24

Mis, Davis

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307572, 3073032, 307246, H03K 17687, H01L 27085, H01L 27108

Patent

active

050755714

ABSTRACT:
A wordline driver circuit is shown for a DRAM, the circuit comprising a PMOS transistor structure having one contact coupled to a wordline, a second contact coupled to a negative voltage supply and a gate coupled to a control input, the transistor having an N-well about the gate, first and second contacts. An isolating structure is positioned about the N-well to enable it to be a separately controlled from surrounding N-well structures. Pulse circuits are coupled to the transistor for applying, when activated, a potential that enables the wordline to transition to a more negative potential. A bias circuit is also provided for biasing the N-well at a first potential and a second lower potential, the second lower potential applied when the pulse circuits are activated. As a result, body effects in the PMOS transistor are minimized while at the same time enabling a boost potential to be applied to the wordline.

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Rajeevakumar et al., "Simple Wordline Boosting Circuit for High Performance CMOS DRAMS", IBM Technical Disclosure Bulletin, vol. 28, No. 6, Nov. 1985, pp. 2660-2662.

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