PMOS single-poly non-volatile memory structure

Details PMOS single-poly non-volatile memory structure PMOS single-poly non-volatile memory structure

1996-10-31

1998-06-02

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518505, 36518529, 257318, 257319, 257320, G11C 1134

Patent

active

057611211

ABSTRACT:
A P-channel single-poly non-volatile memory cell having P+ source and P+ drain regions and a channel extending therebetween is formed in an N-type well. An overlying poly-silicon floating gate is separated from the N-well by a thin oxide layer. A P-type diffusion region is formed in a portion of the N-well underlying the floating gate and is thereby capacitively coupled to the floating gate. Within this P-type diffusion area lies an N-type diffusion area which serves as the control gate for the cell. The P-type diffusion region electrically isolates the control gate from the N-well such that voltages may be applied to the control gate in excess of those applied to the N-well without creating a current path from the control gate to the N-well. Programming is accomplished by coupling a sufficient voltage to the floating gate via the control gate while biasing the source and drain regions so as to cause the tunneling of electrons from the P+ drain region of the cell to the floating gate. In some embodiments, an additional P-type diffusion region underlying the floating gate and separated therefrom by a layer of tunnel oxide serve as an erase gate for the memory cell. In such embodiments, erasing of the cell is accomplished by causing electrons to tunnel from the floating gate to the erase gate.

REFERENCES:
patent: 4404577 (1983-09-01), Cranford, Jr. et al.
patent: 4425631 (1984-01-01), Adam
patent: 4630087 (1986-12-01), Momodomi
patent: 5089433 (1992-02-01), Anand et al.
patent: 5309012 (1994-05-01), Jex et al.

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