PMOS non-volatile latch for storage of redundancy addresses

Details PMOS non-volatile latch for storage of redundancy addresses PMOS non-volatile latch for storage of redundancy addresses

1997-08-15

1998-07-14

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular connection

36518518, 36518526, 36518529, 365218, G11C 1300

Patent

active

057814716

ABSTRACT:
A non-volatile memory latch device includes two PMOS memory cells and a cross-coupled static latch having two PMOS transistors and two NMOS transistors. The floating gates of each PMOS memory cell/transistor pair are coupled together. The control gates of all four PMOS devices are commonly connected to an input. The latch is programmed by applying -3 to -8 volts to the drain of one of the PMOS memory cells, floating the drain of the other PMOS memory cell, and applying 7 to 11 volts to the control gates of all four PMOS devices. The latch is erased by applying 3 to 8 volts to both drains of the PMOS memory cells and -7 to -11 volts to the control gates of all four PMOS devices. Lower programming and erasing voltages are possible with the PMOS latch, as compared with conventional NMOS latches.

REFERENCES:
patent: 4858185 (1989-08-01), Kowshik et al.
patent: 5097449 (1992-03-01), Cuevas
patent: 5648930 (1997-07-01), Randazzo
patent: 5691939 (1997-11-01), Chang et al.
patent: 5706227 (1998-01-01), Chang et al.

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