PMOS Input buffer compatible with logic inputs from an NMOS micr

Details PMOS Input buffer compatible with logic inputs from an NMOS micr PMOS Input buffer compatible with logic inputs from an NMOS micr

1983-07-18

1985-11-12

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307270, 307279, H03K 19094, H03K 3037, H03K 3356

Patent

active

045530513

ABSTRACT:
A PMOS input buffer compatible with logic voltage levels provided by NMOS or TTL microprocessor means uses a limited number of transistors of limited size for driving a load in response to such logic and is adapted for use under widely varying operating conditions.

REFERENCES:
patent: 4000411 (1976-12-01), Sano et al.
patent: 4023050 (1977-05-01), Fox et al.
patent: 4031409 (1977-06-01), Shimada et al.
patent: 4300213 (1981-11-01), Tanimura et al.
Harroun, "Alterable Level Converting Circuit", IBM Tech. Discl. Bull.; vol. 22, No. 8B; pp. 3638-3640; 1/1980.

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