Static information storage and retrieval – Floating gate – Multiple values
Patent
1998-11-30
2000-11-07
Hoang, Huan
Static information storage and retrieval
Floating gate
Multiple values
36518501, 257315, G11C 1604
Patent
active
061445819
ABSTRACT:
A pMOS EEPROM cell includes a source, drain, channel, control gate and well contact. The device is a fully functional single element p-type floating gate MOSFET. A floating gate overlaps the well contact and completely surrounds the drain and source implants. The pMOS cell is written to by means of hot-electron injection, using an intrinsic feedback mechanism to write analog values. Hot electrons are generated in the channel by means of hole impact ionization at the transistor's drain. The pMOS cell is erased by Fowler-Nordheim tunneling. The tunneling voltage is applied only to the well to tunnel electrons from the floating gate. The well-source and well-drain junctions are protected from breakdown by means of guard rings.
REFERENCES:
patent: 3893151 (1975-07-01), Bosselaar et al.
patent: 4420871 (1983-12-01), Scheibe
patent: 4622656 (1986-11-01), Kamiya et al.
patent: 4822750 (1989-04-01), Perlegos et al.
patent: 4935702 (1990-06-01), Mead et al.
patent: 4953928 (1990-09-01), Anderson et al.
patent: 5059920 (1991-10-01), Anderson et al.
patent: 5068622 (1991-11-01), Mead et al.
patent: 5099156 (1992-03-01), Delbruck et al.
patent: 5103116 (1992-04-01), Sivilotti et al.
patent: 5146106 (1992-09-01), Anderson et al.
patent: 5160899 (1992-11-01), Anderson et al.
patent: 5166562 (1992-11-01), Allen et al.
patent: 5319268 (1994-06-01), Lyon et al.
patent: 5331215 (1994-07-01), Allen et al.
patent: 5336936 (1994-08-01), Allen et al.
patent: 5345418 (1994-09-01), Challa
patent: 5376813 (1994-12-01), Delbruck et al.
patent: 5463348 (1995-10-01), Sarpeshkar et al.
patent: 5541878 (1996-07-01), LeMoncheck et al.
patent: 5553030 (1996-09-01), Tedrow et al.
patent: 5627392 (1997-05-01), Diorio et al.
patent: 5666307 (1997-09-01), Chang
patent: 5687118 (1997-11-01), Chang
patent: 5734288 (1998-03-01), Dolazza et al.
patent: 5763912 (1998-06-01), Parat et al.
patent: 5777361 (1998-07-01), Parris et al.
patent: 5825063 (1998-10-01), Diorio et al.
patent: 5841165 (1998-11-01), Chang et al.
patent: 5875126 (1999-02-01), Minch et al.
patent: 5898613 (1999-04-01), Diorio et al.
patent: 5914894 (1999-06-01), Diorio et al.
patent: 5944837 (1999-08-01), Talreja et al.
Diorio, et al., "A High-Resolution Non-Volatile Analog Memory Cell," 1995, IEEE Intl. Symp. on Circuits and Systems, vol. 3, pp. 2233-2236.
Gray, et al., "Analysis and Design of Analog Integrated Circuits", 1984, John Wiley & Sons, pp. 67-71.
Hasler, et al., "An Autozeroing Amplifier Using PFET Hot-Electron Injection", May 12-15 1996, IEEE International Symposium on Circuits and Systems, vol. 3.
Hasler, et al., "An Autozeroing Floating-Gate Amplifier", IEEE Journal of Solid Stae Circuits, pp. 1-15.
Hasler, et al., "Single Transistor Learning Synapse", 1995, Advances in Neural Information Processing Systems 7, MIT Press, pp. 817-824.
Hasler, et al., "Single Transistor Learning Synapse with Long Term Storage," 1995, IEEE Intl. Symp. on Circuits and Systems, vol. 3, pp. 1660-1663.
Hochet, et al., "Implementation of a Learning Kohonen Neuron Based on a New Multilevel Storage Technique", Mar. 1991, IEEE J. Solid-State Circuits, vol. 26, No. 3, pp. 262-267.
Hollis, et al., "A Neural Network Learning Algorithm Tailored for VLSI Implementation", Sep. 1994, IEEE Trans. on Neural Networks, vol. 5, No. 5, pp. 784-791.
Hu, et al., "Hot-Electron-Induced MOSFET Degradation--Model, Monitor, and Improvement", Feb. 1985, IEEE Transactions on Electron Devices, vol. ED-32, No. 2, pp. 375-385.
Ismail, "Neural Information Processing II," 1994, Analog VLSI Signal and Information Process, New York: McGraw-Hill, Inc., pp. 358-413.
Johnson, "Neural Team Bares Silicon Brain", Jul. 3, 1995, Electronic Engineering Times, p. 1 and 31.
Johnson, "Mead Envisions New Design Era", Jul. 17, 1995, Electronic Engineering Times, pp. 1, 37, 38.
Lazzaro, et al., "Winner-Take-All Networks of O(N) Complexity," 1989, in D. S. Touretzky, ed., Advances in Neural Information Processing Systems 1, San Mateo, CA; Morgan Kaufmann, pp. 703-711.
Lazzaro, et al., "Systems Technologies for Silicon Auditory Models," Jun. 1994, IEEE Micro, vol. 14, No. 3, pp. 7-15, T.
Leblebici, et al., "Hot-Carrier Reliability of MOS VLSI Circuits", 1993, Kluwer Academic, 46-49.
Masuoka, et al., "Reviews and Prospects of Non-Volatile Semiconductor Memories," Apr. 1991, IEICE Trans., vol. E 74, No. 4, pp. 868-874.
Mead, et al., Introduction to VLSI Systems, Addison-Wesley Pub. Co., 1980, pp. 1-5.
Mead, "Analog VLSI and Neural Systems", Addison-Wesley Pub. Co., pp. 163-173.
Minch, "A vMOS Soft-Maximum Current Mirror," 1995 IEEE, vol. 3, pp. 2249-2252.
Minch, et al., "Translinear Circuits Using Subthreshold Floating-Gate MOS Transistors," 1996, Analog Integrated Circuits and Signal Processing, vol. 9, No. 2 pp. 167-179.
Sanchez, et al., "Review of Carrier Injection in the Silicon/Silicon-Dioxide System", Jun. 1991, IEEE Proceedings-G, vol. 138, No. 3, pp. 377-389.
Sarpeshkar, et al., "White Noise in MOS Transistors and Resistors," Nov. 1993, IEEE Circuits and Devices, pp. 23-29.
Sarpeshkar, et al., "A Low-Power Wide-Linear-Range Transconductance Amplifier", Analog Integrated Circuits and Signal Processing, in Press, p. 1-28.
Tsividis, et al., "Continuous-Time MOSFET-C Filters in VLSI", Feb. 1986, IEEE Transactions on Circuits and Systems, vol. 33, No. 2, pp. 125-140.
Diorio Christopher J.
Mead Carver A.
California Institute of Technology
Hoang Huan
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