Boots – shoes – and leggings
Patent
1977-05-31
1979-03-20
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 920
Patent
active
041457382
ABSTRACT:
In a data processing system having a plurality of virtual address spaces, a virtual address is translated into a real address for accessing a main memory and the translation result is stored in a translation lookaside buffer, as in a processing system having a single virtual address space. Thereafter, in the case of the same virtual address as the above, the translation lookaside buffer is retrieved to translate the virtual address into a real address. Generally, even in the case of the same virtual addresses, if their virtual address spaces are different, the virtual addresses are translated into different real addresses. However, a control program, a control table or a common subroutine is provided in a common area in which the coordination of virtual and real addresses is always constant even in the case of different virtual address spaces. To enhance the efficiency of utilization of the translation lookaside buffer, common area indicating means is provided, by which the coordination of virtual and real addresses on the translation lookaside buffer is registered so that it can be used in common to a plurality of virtual address spaces.
REFERENCES:
patent: 3825904 (1974-07-01), Burk et al.
patent: 4004278 (1977-01-01), Nagashima
Inoue Koichi
Nonogaki Hajime
Shimizu Kazuyuki
Urakawa Tatsuo
Fujitsu Limited
Zache Raulfe B.
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