Plural processor inferencing system and method

Details Plural processor inferencing system and method Plural processor inferencing system and method

1988-06-28

1991-01-01

MacDonald, Allen

Boots, shoes, and leggings

364133, G06F 1518

Patent

active

049823400

ABSTRACT:
An inference processing system comprises a plurality of processors assigned for nodes of a semantic network respectively to carry out parallel processing. Each of the processors stores tables and linking information. The tables are made by arranging rules and prepared for goals respectively. Each table contains the names of links to follow when a certain goal is given and markers for specifying the kinds of the links. In the table, the link names and markers are set as outputs with respect to the given goal as an input. The linking information contains information of links connected to a node for which a corresponding one of the processors is assigned. When the goal and a marker are inputted to any one of the processors, the processor finds an output marker and output links in the tables and linking information and outputs the output marker to the output links, thus achieving an inference process.

REFERENCES:
patent: 4815005 (1989-03-01), Oyanagi et al.
National Computer Conference 1986; L. Bic; "Dataflow Architectures for Knowledge Representation Systems".
Proceedings of First Annual National Conference on Artificial Intelligence; S. E. Fahlman, "Design Sketch for a Million-Element Netl Machine"; Aug. 1980.

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