Plural-order sigma-delta analog-to-digital converter using both

Details Plural-order sigma-delta analog-to-digital converter using both Plural-order sigma-delta analog-to-digital converter using both

1990-11-01

1992-01-28

Pellinen, A. D.

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

341118, H03M 302, H03M 304, H03M 106

Patent

active

050847023

ABSTRACT:
An oversampling converter of a type using a plural-order, plural-stage sigma-delta modulator, the output signal to the decimating filter of which modulator has the quantization noise contribution of a number of its plurality of stages suppressed therein, uses single-bit quantization in those stages, and the modulator uses single-bit quantization in those stages. Those stages each employ digital-to-analog converters with single-bit resolution in their feedback connections to avoid non-linearity problems. Another sigma-delta converter stage, the quantization noise of which appears in substantial amount in the converter output signal to the decimating filter, uses quantization having multiple-bit resolution to help increase the resolution of the oversampling converter overall. This other sigma-delta converter stage also employs a digital-to-analog converter with single-bit resolution in its feedback connection in order to avoid non-linearity problems, with additional circuitry being used to compensate for the digital-to-analog converter having single-bit, rather than multiple-bit, resolution.

REFERENCES:
patent: 4843390 (1989-06-01), Van Bavel et al.
patent: 4860012 (1989-08-01), Rich et al.
patent: 4862169 (1989-08-01), Van Bavel et al.
patent: 4876543 (1989-10-01), Van Bavel
patent: 4951052 (1990-08-01), Jacob et al.
patent: 4999625 (1991-03-01), Thompson
"An Improved Sigma-Delta Modulator Architecture", Proceedings of the IEEE International Symposium on Circuits & Systems, pp. 372-375, May 1990, T. C. Leslie & B. Singh.
"A 16-Bit oversampling A-D Conversion Technology Using Triple Integration Noise Shaping", IEEE Journal of Solid State Circuits, vol. SC-22, No. 6, pp. 921-929, Dec. 1987, Y. Matsuya et al.
"A 16-Bit 160 kHz CMOS A/D Converter Using Sigma-Delta Modulation", Proceedings 1988 Custom Integrated Circuits Conference, Sep. 6, 1988, M. Rebeschini et al.
"A 13-Bit ISDN-Band ADC Using Two-Stage Third Order Noise Shaping", Proceedings 1988 Custom Integrated Circuit Conference, pp. 21.2.1-21.2.4, Jun. 1988, L. Longo and M. A. Copeland.

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