Plural operand buses of intermediate widths coupling to narrower

Details Plural operand buses of intermediate widths coupling to narrower Plural operand buses of intermediate widths coupling to narrower

1997-08-15

1999-05-11

Kim, Kenneth S.

395306, 395563, 39580023, G06F13/40

Patent

active

059037725

ABSTRACT:
A processor core for supporting the concurrent execution of mixed integer and floating point operations includes integer functional units (110) utilizing 32-bit operand data and a floating point functional unit (22) utilizing up to 82-bit operand data. Eight operand busses (30, 31) connect to the functional units to furnish operand data, and five result busses (32) are connected to the functional units to return results. The width of the operand busses is 41 bits, which is sufficient to communicate either integer or floating point data. This is done using an instruction decoder (18) to apportion a floating point operation which operates on 82-bit floating point operand data into multiple suboperations each associated with a 41-bit suboperand. The operand busses and result busses have an expanded data-handling dimension from the standard integer data width of 32 bits to 41 bits for handling the floating point operands. The floating point functional unit recombines the suboperand data into 82-bits for execution of the floating point operation, and partitions the 82-bit result for output to the result busses. In addition, the excess capacity of the result busses during integer transfers is used to communicate integer flags.

REFERENCES:
patent: 4823260 (1989-04-01), Imel et al.
patent: 5067003 (1991-11-01), Okamura
patent: 5155817 (1992-10-01), Kishigami et al.
patent: 5337415 (1994-08-01), DeLano et al.
patent: 5438668 (1995-08-01), Coon et al.
patent: 5465373 (1995-11-01), Kahle et al.
patent: 5467473 (1995-11-01), Kahle et al.
patent: 5488710 (1996-01-01), Sato et al.
patent: 5546551 (1996-08-01), Kohn
patent: 5691949 (1997-11-01), Hively et al.
Mike Johnson, "Superscalar Microprocessor Design", (Prentice-Hall series in innovative technology), .COPYRGT.1991. (Copy of book has been place in USPTO Library).
R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", Part 2 Regions of Computer Space, Section 3 Concurrency: Single-Processor System, IBM Journal, vol. 11, Jan. 1967, pp.293-305.
U.S. Patent Application Serial No. 08/145,902 filed Oct. 29, 1993 entitled "Speculative Instruction Queue and Method Therefor Particularly Suitable for Variable Byte-Length Instructions"---David B. Witt, Attorney Docket No. M-2279 US.
U.S. Patent Application Serial No. 08/145,905 filed Oct. 29, 1993 entitled "Pre-Decoded Instruction Cache and Method Therefor Particularly Suitable for Variable Byte-Length Instructions"---David B. Witt and Michael D. Goddard, Attorney Docket M-2278 US.
U.S. Patent Application Serial No. 08/146,383 filed Oct. 29, 1993 entitled "Superscalar Instruction Decoder"---David B. Witt and Michael D. Goddard, Attorney Docket No. 2280 US.
D.W. Anderson, F.J. Sparacio, F.M. Tomasulo, "The IBM System/360 Model 91", Machine Philosophy and Instruction-handling, Chapter 18, Part 2 Regions of Computer Space, Section 3 Concurrency: Single-Processor System, IBM Journal, vol. 11, Jan. 1967, pp. 276-292.
U.S. Patent Application Serial No. 07/929770 filed Apr. 12, l992 entitled "Instruction Decoder and Superscalar Processor Utilizing Same"---David B. Witt and William M. Johnson.
Michael Slater, "AMD's K5 Designed to Outrun Pentium", Microprocessor Report, vol. 8, No. 14, Oct. 24, l994, pp. 1,6-11.
Brian Case, "AMD Unveils First Superscalar 29K Core", Microprocessor Report, vol. 8, No. 14, Oct. 24, l994, pp. 23-26.
Gurindar S. Sohi, "Instruction Issue Logic for High-Performance, Interrruptible, Multiply Functional Unit, Pipelined Computers", IEEE Transaction on Computers, vol. 39, No. 3, .COPYRGT.1990, pp. 349-359.
Bruce D. Lightner and Gene Hill, "The Metaflow Lightning Chipset", IEEE Proceedings ConpCom Spring '91, Feb. 1991, pp. 13-18.
R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal, Jan. 1967, vol. 11, pp. 25-32.
IBM Technical Disclosure Bulletin, "High Speed Buffer with Dual Directories", vol. 26, No. 12, May 1984, pp. 6264-6265.
IBM Technical Disclosure Bulletin, "System/370 Emulator Assist Processor for a Reduced Instruction Set Computer", vol. 30, No. 10, Mar. 1988, pp. 308-309.
Shreekant S. Thakkar and William E. Hostmann, "An Instruction Pitch Unit for a Graph Reduction Machine", IEEE, 1986, pp. 82-91.
Toyohiko Yoshida, et al., "The Approach to Multiple Instruction Execution in the GMICRO/400 Processor", .COPYRGT.1991, pp. 185-195.
Val Popescu, "The Metaflow Architecture", IEEE Micro, Jun. 1991, pp. 10-13 and 63-73.
IBM Technical Disclosure Bulletin, "Variable-Performance Processors", vol. 17, No. 12, May 1975, pp. 3708-3710.
Tom R. Halfhill, "AMD K6 Takes on Intel P6", BYTE magazine, Jan. 1996, pp. 67-68,70, and 72.

Affiliated with

Also associated with

Rating

Plural operand buses of intermediate widths coupling to narrower does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Plural operand buses of intermediate widths coupling to narrower, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Plural operand buses of intermediate widths coupling to narrower will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-254559