Plural microcode control memory

Details Plural microcode control memory Plural microcode control memory

1979-09-24

1984-07-10

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 900, G06F 922

Patent

active

044596669

ABSTRACT:
A microcode control memory having a first memory for receiving initial instructions is shown in combination with at least one additional memory for executing multistep control functions in a computer system. The first memory receives all initial control instructions from an instruction stack and produces the appropriate control output. Simultaneously as part of the initial instruction, a memory select network receives a control bit so that an output select network connected to the output of all memories passes the output from the first memory to the output register. Single step instructions are processed continuously this way. Multistep instructions are performed by using a portion of the output from the first memory to serve as the address selection in one of the other memories. When a multistep instruction is completed, the output select network again selects the output from the first memory for gating to the output register. The memory select network provides a control for the selection of the output of the first or any other memory at the same time that the memory is generating an output from an input address.

REFERENCES:
patent: 3651476 (1972-03-01), Metz et al.
patent: 3768075 (1973-10-01), Reitsma et al.
patent: 4008462 (1977-02-01), Kanda
patent: 4080648 (1978-03-01), Asano et al.
patent: 4124891 (1978-11-01), Weller et al.
patent: 4153937 (1979-05-01), Poland
patent: 4156279 (1979-05-01), Wilhite

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