Plural memory controller apparatus

Details Plural memory controller apparatus Plural memory controller apparatus

1975-07-31

1977-04-05

Shaw, Gareth D.

Communications: electrical

Digital comparator systems

G06F 1300, G06F 920

Patent

active

040165450

ABSTRACT:
A general purpose digital computer whose architecture provides a set of pointer registers at each memory chip to perform stack operations previously performed on the CPU chip. Bidirectional lines interconnect the CPU chip and the memory chips for transmission and reception of data and control signals. Each memory chip has a circuit for incrementing or decrementing the pointer registers in response to a control signal without the transmission of a data signal from the CPU chip to perform a series of stack operations in the memory chip. Addressable registers are provided in each memory chip for identifying the memory chip (PAGE), storing a mode vector (MODE), and counting the number of times the memory controller was addressed (TIME).

REFERENCES:
patent: 3737871 (1973-06-01), Katzman
patent: 3778776 (1973-12-01), Hakozaki
patent: 3818460 (1974-06-01), Beard et al.
patent: 3889243 (1975-06-01), Drimak
patent: 3975714 (1976-08-01), Weber et al.

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