Plural circuit selection using role reversing control inputs

Details Plural circuit selection using role reversing control inputs Plural circuit selection using role reversing control inputs

1999-11-19

2002-05-21

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

C375S377000, C370S216000, C710S021000, C710S038000, C710S261000, C713S500000, C713S502000, C713S600000

Reexamination Certificate

active

06393081

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
Circuits that communicate data may have data inputs for inputting data, data outputs for outputting data, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication.
2. Description of the Related Art
In
FIG. 1
, a conventional circuit
110
has a data input bus
101
, a data output bus
102
, clock input bus
103
, and mode input bus
104
. The circuit
110
responds to the clock input and mode input to either, (1) remain in an idle state where no data communication occurs, or (2) enter a data communication state where data is communicated between the circuit's data input and/or data output.
While the circuit example in
FIG. 1
is intentionally simple for clarification, its input/output signaling model, consisting of data input, data output, clock input, and control input signals, could represent more complex circuits. For example the circuit model could represent IEEE 1149.1 test access port circuits implemented in integrated circuits or included in the design layout or data base of intellectual property core circuits, such as CPUs and DSPs, for use as sub-circuits within an integrated circuit. Further, the example circuit model could represent, in general any type, of data communication circuits, such as shift registers, synchronously operated memories, micro-controllers, CPUs, DSPs, analog to digital converters whereby the data input is understood to be analog signal data input, or digital to analog converters whereby the data output is understood to be analog signal data output.
In
FIG. 2
, the clock signals input on bus
103
time the circuit to operate, in response to mode input on bus
104
, in either an idle state
202
or communicate state
204
. The circuit
110
will be in the idle state
202
during clocks signals occurring while the mode signal on bus
104
is low, and will transition to the communicate state
204
during a clock signal occurring when the mode signal on bus
104
is high. The circuit will remain in the communicate state
204
during clock signals occurring while the mode signal is high. The circuit will return to the idle state
202
during a clock signal occurring when the mode signal is low.
In the idle state, no data communication occurs in the circuit from the data input and/or data output. In the communicate state, data communication occurs in the circuit
110
from the data input and/or data output. It should be understood that the state diagram of
FIG. 2
is intentionally simplified to clarify the description of the invention. A more complex state diagram, having at least an idle state and at least a data communication state could have been used as well. For example, the state diagram of the above mentioned IEEE 1149.1 test access port circuit contains an idle state (RTIDLE) and data communication states (DR-Shift & IR-Shift) and could have been used. However, for the purpose of describing the invention, the
FIG. 2
state diagram is adequate.
In
FIG. 3
, circuit
110
operates according to the state diagram of FIG.
2
. In
FIG. 3
, the circuit
110
remains in the idle state during clock signals occurring while the mode signal is low. The circuit
110
transitions into the communicate state during the first clock signal that occurs after the mode signal goes high. The circuit remains in the communicate state during clocks occurring while the mode signal is high. The circuit transitions back to the idle state during the first clock that occurs after the mode signal goes back low.
The communicate state could operate a circuit as shown in
FIG. 1
to: (1) transfer data inputs directly, through an enabled buffer or switch, to data outputs of the circuit; (2) transfer data inputs to the data outputs via intermediate storage circuitry within the circuit; (3) input data to the circuit, process the input data using processing circuitry within the circuit, and output the processed data; (4) input data to the circuit and store the data in a internal memory; (5) output data previously stored in an internal memory; or (6) input and store data while outputting previously stored data.
In this specification, the mode input is evaluated on the rising edge of the clock input to determine state transitions. Also, the clock input will operate as a low to high and high to low pulse that occurs during times when the mode input is in a steady state one or zero logic condition. While a rising edge clock pulse convention is used in this description, a falling edge clock pulse convention could be used as well. Also the mode inputs may be inverted from what is shown in
FIG. 3
without departing from the nature of the present invention.
SUMMARY OF THE INVENTION
The present invention provides a way to communicate data through two separate circuits or circuit groups, each having clock and mode inputs, by sharing and reversing the role of the clock and mode inputs.
A first advantage of the present invention is that it provides a method of augmenting a second data communication protocol on a pair of control signals, clock and mode, originally designed to use only a first data communication protocol. A second advantage of the present invention is that it provides a method of designing new circuits to utilize first and second data communication protocols on the same control signal wiring. A third advantage of the present invention is that it reduces the wiring required for communicating data through separate circuits, since the clock and mode input wiring, as well as the data input and data output wiring, may be shared between the separate circuits.
A fourth advantage of the present invention is that it provides a method of accessing backup or redundant circuitry in a fault tolerant system environment by reuse of the same control bussing for accessing either the primary or backup circuitry. A fifth advantage of the present invention is that it provides a method of accessing shadow circuitry, i.e. special circuitry used by the manufacturer or end user for test, debug, diagnostics, emulation, or software development, by reuse of the same control bussing for accessing either the functional or shadow circuitry.
The circuits described herein could represent; (1) a printed circuit board, (2) an integrated circuit, or (3) individual sub-circuits within an integrated circuit.


REFERENCES:
patent: 5594896 (1997-01-01), Carlson
patent: 5659508 (1997-08-01), Lamphier et al.
patent: 5745742 (1998-04-01), Selway et al.
patent: 5959915 (1999-09-01), Kwon et al.
patent: 5991888 (1999-11-01), Faulkner et al.
patent: 6029061 (2000-02-01), Kohlschmidt
patent: 6122762 (2000-09-01), Kim
patent: 6209022 (2001-03-01), Sotek et al.

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