Plural-channel decimation filter, as for sigma-delta analog-to-d

Details Plural-channel decimation filter, as for sigma-delta analog-to-d Plural-channel decimation filter, as for sigma-delta analog-to-d

1991-07-05

1993-07-06

Nguyen, Long T.

Boots, shoes, and leggings

G06F 1531

Patent

active

052260011

ABSTRACT:
A decimation filter in which two filtering processes are carried out on a time-division-multiplexed basis using kernels that are sampled-data representations of triangular waves, one of which triangular waves decrements while the other increments, or vice versa. A digital multiplier receives the time-interleaved kernels as a multiplicand and receives as a multiplier a stream of bits supplied at a rate that is one-quarter that of the filter clock pulses. The digital multiplier applies its product output signal to the addend input port of a parallel-bit adder. The sum output port of this adder connects to a cascade connection of first, second, third and fourth clocked latches. The signal from the output port of the fourth clocked latch is supplied to the augend input port of the adder except during the first four clock pulse durations after the kernel values reach maxima. The signal from the output port of the third clocked latch is supplied to the augend input port of the adder during zeroeth and second clock pulse durations after the kernel values reach maxima, and arithmetic zero is supplied to the augend input port of the adder during the first and third clock pulse durations after the kernel values reach maxima. First and second output signals for the decimation filter are extracted from the output ports of the second and fourth clocked latches. This decimation filter can be used on a single-channel or dual-channel basis.

REFERENCES:
patent: 5126961 (1992-06-01), Garverick

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