Plural cache architecture for real time multitasking

Details Plural cache architecture for real time multitasking Plural cache architecture for real time multitasking

1989-11-09

1992-08-25

Bowler, Alyssa H.

Static information storage and retrieval

Magnetic bubbles

Guide structure

365 49, G11C 700, G06F 1300, G06F 1200

Patent

active

051426714

ABSTRACT:
In a data processor, when there is any cache memory not being activated after the whole data processor has been activated, a signal is delivered to a bus driver and then a data processing unit is connected to a system bus. During the period from when the whole data processor has been activated to when all the cache memories start to be activated, the data processing unit is connected to the system bus so that data can be transmitted/received between the data processing unit and peripheral devices.

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