Plural-bit-per-cell read-only memory

Details Plural-bit-per-cell read-only memory Plural-bit-per-cell read-only memory

1984-09-17

1987-03-24

Moffitt, James W.

Static information storage and retrieval

Read only systems

Semiconductive

365168, 365210, G11C 1156, G11C 1700, H01L 2710

Patent

active

046530231

ABSTRACT:
A plural-bit-per-cell read-only memory constituted by a memory cell array (1), reference cell array (2A, 2B, 2C), and related circuits. In the memory cell array (1), a low resistance ground line (17) crossing the diffusion layer in parallel with the bit lines (15) is arranged for each predetermined length of the diffusion layer, which is used as a common grounding route to the low resistance ground line (17). The reference cell array (2A) includes a plurality of reference cells (211, 212, . . . 21n), and the arrangement of the reference cells (211, 212, . . . 21n) corresponds to the arrangement of the plural-bit memory cells (14) within the predetermined length of the diffusion layer in the memory cells array (1). The transconductance of the reference cells is predetermined in correspondence with the reference voltage values (REF1, REF2, REF3). A column address signal which selects a plural-bit memory cell (14) also selects one of the reference cells (211, 212, . . . 21n) which corresponds to the plural-bit memory cell (14) selected by the column address signal. Thus, in generation of reference voltages (REF1, REF2, REF3), the reference voltage value is corrected taking into consideration the influence of resistance of the diffusion layer according to the location of the plural-bit memory cell (14) selected by the column address signal.

REFERENCES:
patent: 4415992 (1983-11-01), Adlhoch
patent: 4449203 (1984-05-01), Adlhoch
patent: 4503518 (1985-03-01), Iwahashi
Electronics International, vol. 56, No. 6, Mar. 24th, 1983, pp. 121-123, New York, US; B. Donoghue et al.; "Variable Geometry Packs 2 Bits Into Every ROM Cell" *Figures 1, 3*.
Electronics International, vol. 55, No. 11, Jun. 2nd, 1982, pp. 141-145, New York, US; F. A. Scherpenberg et al.; "Asynchronous Circuits Accelerate Access to 256-K Read-Only Memory" *Figures 1; p. 142, lines 8-12*.
J. A. Bayliss et al., "The Interface Processor for the Intel VLSI 423 32-Bit Computer", IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 5, 1981.

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