Plug protection process for use in the manufacture of embedded d

Details Plug protection process for use in the manufacture of embedded d Plug protection process for use in the manufacture of embedded d

1997-04-25

1998-06-30

Tsai, Jey

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

438240, H01G 706

Patent

active

057733147

ABSTRACT:
A method for forming an embedded DRAM structure along with tungsten plugged MOS transistor devices begins by forming capacitor tungsten plugs (46) and bit-line tungsten plugs (44). A bottom capacitor electrode (48b) is formed to protect the tungsten plug (46). Simultaneously, an optionally-removable barrier region (48a) is formed to protect the plug (44). A capacitor dielectric (52) is deposited and oxygen annealed to form a ferroelectric capacitor material. The barrier (48a) and the lower electrode (48b) protect all of the tungsten plugs (46 and 44) from being adversely oxidized by the oxygen anneal. A top electrode (54 and 56) of the ferroelectric capacitor is then deposited, lithographically patterned, and etched. The lithographic patterning and etching of the top electrode may also be further utilized to remove the barrier region (48a).

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