Plug contact with antifuse

Details Plug contact with antifuse Plug contact with antifuse

1991-05-03

1993-08-03

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

257 50, 257751, 257752, 257764, H01L 2948

Patent

active

052332179

ABSTRACT:
An antifuse particularly suitable for submicron geometries is presented. The antifuse is formed between a silicon layer, which could be a doped region of the semiconductor substrate, an epitaxial layer or a polysilicon layer, and an upper metal interconnection layer. In contact holes in a silicon dioxide layer insulating the silicon and metal interconnection layers from each other, the antifuses have a thick refractory metal layer having a top surface approximately at the same level as the top surface of the insulating layer. Depending upon the process used to deposit the refractory metal layer, a thin adhesion layer may be located immediately below the refractory metal layer. Between the underlying silicon layer and upper interconnection layer, a thin semiconductor material layer of amorphous silicon may be located either below the refractory metal layer or above it. At its bottom, the interconnection layer also has a barrier layer to prevent any intermixing between the amorphous silicon layer and the metal interconnection layer.

REFERENCES:
patent: 3571673 (1971-03-01), Ovshinsky
patent: 3675090 (1972-07-01), Neale
patent: 3877049 (1975-04-01), Buckley
patent: 4361599 (1982-11-01), Wourms
patent: 4442507 (1984-04-01), Roesner
patent: 4458297 (1984-07-01), Stopper et al.
patent: 4796074 (1989-01-01), Roesner
patent: 4914055 (1990-04-01), Gordon et al.

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