PLL with loop bandwidth calibration circuit

Details PLL with loop bandwidth calibration circuit PLL with loop bandwidth calibration circuit

2009-04-21

2011-10-04

Chang, Joseph (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S00100A, C331S017000, C331S025000

Reexamination Certificate

active

08031008

ABSTRACT:
A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.

REFERENCES:
patent: 2009/0174491 (2009-07-01), Wang et al.
patent: 2009/0206941 (2009-08-01), Wang et al.

Affiliated with

Also associated with

Rating

PLL with loop bandwidth calibration circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with PLL with loop bandwidth calibration circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PLL with loop bandwidth calibration circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4292018