PLL using a multi-phase frequency correction circuit in place of

Details PLL using a multi-phase frequency correction circuit in place of PLL using a multi-phase frequency correction circuit in place of

1991-05-21

1992-07-21

Grimm, Siegfried H.

Oscillators

Relaxation oscillators

328155, 331 17, 331 25, 331 34, H03L 7099

Patent

active

051326337

ABSTRACT:
A phase-locked loop generates a periodic clock signal which matches the frequency of an input signal, such as digital data signals transmitted over an optical fiber. A ring oscillator or other clock generator generates a 2N-phase reference clock signal with a reference frequency f.sub.0, where N is a positive, odd integer having a value of at least three. The 2N reference clock phasor signals have evenly distributed phases. A waveform generator generates a 2N-phase control signal having a frequency .vertline.f.sub.M .vertline. which corresponds to the difference between the input signal's frequency and the reference frequency f.sub.0. The value of f.sub.M is greater than zero when the input signal's frequency is higher than f.sub.0, and it is less than zero when the input signal's frequency is less than f.sub.O. A frequency correction circuit (FCC) generates an output clock signal havng an output frequency which is equal to f.sub.0 +f.sub.M. The frequency correction circuit modulates each reference phasor signal with a corresponding one of the 2N control phasor signals, and then combines the result modulated reference phasor signals to generate the output clock signal. A phase detector continually compares the output frequency with the input signals's frequency, and adjusts the frequency f.sub.M of the 2N control phasor signals so that the output frequency closely matches the input frequency. Typically, the reference frequency differs from the input frequency by no more than a factor of one in a thousand.

REFERENCES:
patent: 5059924 (1991-10-01), Jennings
patent: 5068628 (1991-11-01), Ghoshal

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