PLL timing generator with voltage controlled oscillator

Details PLL timing generator with voltage controlled oscillator PLL timing generator with voltage controlled oscillator

1995-02-16

1997-04-08

Pascal, Robert

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 57, 327156, 327158, 327291, H03K 3017, H03K 504

Patent

active

056191707

ABSTRACT:
A phase lock loop timing generator including a voltage controlled oscillator as a current-limited ring oscillator composed of multistage inverters connected in series in a ring form using a phase lock loop. From nodes of the inverters, .phi.0 to .phi.8 signals are obtained and an AND or OR of the signals are calculated to generate an internal timing. The obtained timing pulse is defined by % of a clock cycle of a reference clock signal and thus a timing depending on an external cycle can be set. Further, a timing prior to the clock edge of the reference clock signal can be generated and by using this timing, an effective current cut of an input buffer can be performed. Hence, timing generation proportional to the external clock cycle without being affected by a production process or the like provides a flexible timing design.

REFERENCES:
patent: 4061975 (1977-12-01), Sugai
patent: 4713621 (1987-12-01), Nakamura et al.
patent: 4797585 (1989-01-01), Segawa et al.
patent: 5018169 (1991-05-01), Wong et al.
patent: 5179294 (1993-01-01), Bechade et al.
patent: 5264737 (1993-11-01), Oikawa
patent: 5331295 (1994-06-01), Jelinek et al.
patent: 5448205 (1995-09-01), Rothermel
"Three-phase clock from reference clock using TTL" by Afzal, Electronic Engineering Jun. 1979, vol. 51, No. 624, p. 35.
"Delay Line Applications" by J.C. Rogers et al. IBM Tech. Disc., vol. 5, No. 1, Jun. 1962.

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