PLL system clock generator with instantaneous clock frequency sh

Details PLL system clock generator with instantaneous clock frequency sh PLL system clock generator with instantaneous clock frequency sh

1994-09-02

1999-11-09

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327117, 377 47, H03L 718

Patent

active

059822104

ABSTRACT:
The present invention provides a phase locked loop (PLL) clock generator for a digital system. The PLL clock generator is capable of an instantaneous transition between a high frequency and a low frequency, corresponding to an active mode and a slow mode, and vice versa The PLL clock generator includes a phase locking circuit, a frequency changer coupled to the output of the phase locking circuit, and a frequency controller coupled to the frequency changer. The frequency changer is capable of instantaneously changing the frequency of a first clock signal received from the phase locking circuit. The frequency controller is responsible for controlling the frequency at the output of the frequency changer. The frequency controller is responsive to a control signal which is used to transition the PLL clock generator from an active mode to a slow mode and vice versa In one embodiment, the phase locking circuit generates the first clock signal in response to a reference clock signal and a feedback clock signal. The frequency changer includes a first divider for generating a global clock signal in response to the first clock signal, and a second divider for generating a peripheral clock signal and a feedback signal in response to the global clock signal The frequency controller, responsive to the control signal is used to change the divisors of the first and second dividers simultaneously, thus instantaneously transitioning the PLL circuit between the active mode and slow mode.

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