PLL synthesizer radio paging receiver capable of reducing an ave

Details PLL synthesizer radio paging receiver capable of reducing an ave PLL synthesizer radio paging receiver capable of reducing an ave

1995-06-30

1998-06-02

Pham, Chi H.

Telecommunications

Receiver or analog modulated signal frequency converter

With particular receiver circuit

4551651, 455260, 455266, H04B 116

Patent

active

057616175

ABSTRACT:
In a radio paging receiver which is for receiving call signals and which includes a control section (5) for making each of a PLL synthesizer section (4), a frequency converter section (2), and a demodulator section (3) carry out intermittent operation selectively in a short intermittent operation cycle synchronized with the call signals and in a long intermittent operation cycle longer than the short intermittent operation cycle, the PLL synthesizer has first and second loop filters (7 and 8) having first and second time constants, respectively. The second time constant is larger than the first time constant. One of the first and the second loop filters is selectively operable at a time. The control section further controls the first and the second loop filters so that the first loop filter is selectively operable when the contol section makes each of the PLL synthesizer section, the frequency converter section, and the demodulator section carry out the intermittent operation in the short intermittent operation cycle and that the second loop filter is selectively operable when the contol section makes each of the PLL synthesizer section, the frequency converter section, and the demodulator section carry out the intermittent operation in the long intermittent operation cycle.

REFERENCES:
patent: 4539707 (1985-09-01), Jacobs et al.
patent: 4596046 (1986-06-01), Richardson et al.
patent: 5058204 (1991-10-01), Tahernia et al.
patent: 5175729 (1992-12-01), Borras et al.

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