PLL synthesizer having frequency dividers with reset control

Details PLL synthesizer having frequency dividers with reset control PLL synthesizer having frequency dividers with reset control

1993-07-12

1994-04-19

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 14, 331 16, 331 25, 331DIG2, H03L 7089, H03L 7095, H03L 718

Patent

active

053049543

ABSTRACT:
This invention aims at providing a PLL synthesizer circuit that can shorten lock-up time while sufficiently securing a time constant of a low-pass filter, and has a structure wherein a phase comparator 3 outputs output signals .phi.R and .phi.P on the basis of a reference signal fr output from a reference frequency divider 2, and a comparison signal fp output from a comparison frequency divider 4; the output signals .phi.R and .phi.P are negatively fed back to the comparison frequency divider 4 through a charge pump 5, a low-pass filter 6 and a voltage controlled oscillator 7, and a lock detection circuit 8 outputs a lock signal LD when in a locked state. When an output signal SVCO of the voltage control oscillator 7 coincides with a set frequency, when the lock detection circuit 8 does not output the lock signal LD, a reset circuit 15 outputs a reset signal PC to the reference frequency divider 2 and to the comparison frequency divider 4, and the reset signal PC brings the phase of the reference signal fr into conformity with the phase of the comparison signal fp.

REFERENCES:
patent: 4817199 (1989-03-01), Wallraff
patent: 5113152 (1992-05-01), Norimatsu

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