PLL synthesizer circuit

Details PLL synthesizer circuit PLL synthesizer circuit

1999-11-22

2001-09-11

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S157000, C327S148000, C327S156000, C331S00100A

Reexamination Certificate

active

06288583

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PLL synthesizer circuit for preferable use in an RDS radio receiver or the like requiring fast switching of its local oscillation frequency when changing receiving broadcasting stations.
2. Description of the Related Art
Generally, electric tuner radio receivers generate a local oscillation signal in PLL (phase locked loop) synthesizer circuits, as shown in FIG.
1
. As a PLL included in the PLL synthesizer circuits is a conventional art, ordinary operation of a PLL synthesizer circuit will not be described here, but PLL operation to change the frequency of a local oscillation signal in the PLL synthesizer circuit will be described.
Initially, based on the frequency of a broadcasting station to be received, dividing data on the dividing ratio of the frequency is supplied to a programmable divider
1
. Based on the dividing data, the dividing number of the programmable divider
1
is changed, and the phase of an output from the program divider
1
is changed accordingly. Then, a phase comparator
3
compares phases of a reference signal from a reference signal generator
2
and of an output from the programmable divider
1
for every cycle of a reference signal, and a charge pump circuit
4
generates an error signal according to the phase difference. The error signal is smoothed by a loop filter
5
into a DC voltage, which is to be referred to as a control voltage in a VCO (a voltage control oscillation circuit)
6
. The oscillation frequency of the VCO
6
is changed according to the control voltage. The VCO
6
is repeatedly modified as described above such that an output phase of the programmable divider
1
gradually becomes closer to the phase of the reference signal. Finally, when the above two phases become identical, the PLL circuit is locked, and the oscillation frequency of the VCO
6
is set at a frequency in accordance with the dividing data, i.e., the frequency of the receiving broadcasting station.
An output signal (a local oscillation signal) from the VCO
6
is mixed with an RF amplifying signal in a mixer into an intermediate frequency (IF) signal. An IF signal always has a constant frequency, while the local oscillation frequency is changed according to the receiving broadcasting station.
Conventionally, in order to change an output frequency of a PLL synthesizer circuit, operation must be repeatedly performed, including phase comparison between a reference signal and an output from the programmable divider
1
, and output of an erroneous signal based on the comparison result. This operation is generally repeated a few hundred times after the start of frequency change until completion of locking the PLL, each every cycle of a reference frequency. Therefore, for a 50 kHz reference frequency, 20 &mgr;sec is required to complete one complete process of this operation (i.e., from phase comparison to change of the VCO oscillation frequency), and thus (20 &mgr;sec×a few hundred times) elapses from the start of the change to the completion of locking the PLL.
In radio broadcasting in Europe, traffic information is commonly superimposed on general broadcasting. Such broadcasting with superimposed traffic information is known as RDS (Radio Data System) Broadcasting, and reception requires that a receiver have a dedicated tuner for the traffic information. Such RDS tuners have various additional functions utilizing traffic information. One example of such functions may be a search for a substitutional station to replace a currently receiving station becoming hardly receivable, using program identifying data contained in such traffic information. To achieve this function, such a search must be continually applied while any broadcasting station is being received to ensure constant availability of a potential substitutional station. In such a search, the receiving frequency must be swiftly changed from that of the current station to that of the potential substitutional station, RDS data on and receiving condition of the potential substitutional station must be checked, and the receiver frequency must be swiftly changed back from the one for the potential substitutional station to the one for the current station.
However, as the PLL synthesizer circuit of
FIG. 1
requires a long time from the beginning of frequency change to completion of locking of the PLL, a long time is required to complete frequency change to one for a potential substitutional station and back to the current station. This may lead to a problem such that reception of the current station is temporarily cut off, causing unfavorable reception conditions for the listener.
SUMMARY OF THE INVENTION
The present invention aims to provide a PLL synthesizer circuit capable of completing locking of the PLL in a reduced time period compared to a conventional one.
According to the present invention, an output frequency of the PLL circuit is forcibly changed by the frequency change circuit. Therefore, change of the frequencies of the PLL circuit, and thus of receiving stations by the radio receiver, can be completed in a shorter time. As change to a substitutional station can be swiftly achieved, particularly in a substitutional station search by an RDS radio receiver, listener annoyance can be prevented.
Further, when the frequency change circuit is not operating for frequency change, supply of system clocks to the frequency change circuit is preferably halted to prevent noise and to avoid deterioration of the properties of an IF circuit in a radio receiver or the like due to such noise from the frequency change circuit.
Also, preferably, a gate time (a measurement time) for the frequency counter in the frequency change circuit is set by the gate time set circuit according to a difference between a count value counted by the frequency counter and the dividing data supplied from the deciding portion. With the above, a gate time for the frequency counter can be set short when frequency detection accuracy is not highly required, and longer when it is required. Consequently, a processing time for the frequency change circuit can be reduced, while an accurate frequency can be output from the PLL.
Further, preferably, the frequency change circuit controls the PLL circuit so as to output a frequency at a predetermined value in response to a reset request signal, which is generated when turning on the power and so on. With the above, the VCO control voltage for the PLL circuit can be forcibly raised so that erroneous operation due to deadlock situation, which might otherwise be caused when turning on the power, can be prevented.
Further, preferably, the time constant of the loop filter is set smaller when the frequency change circuit carries out operation for changing an output frequency of the PLL circuit than when it does not. With the above, the frequency change by the frequency change circuit can be accelerated.


REFERENCES:
patent: 4562410 (1985-12-01), O'Rouke
patent: 5334952 (1994-08-01), Maddy et al.
patent: 0 768 756 A2 (1997-04-01), None
patent: 0 595 787 A2 (1997-05-01), None
patent: 0 907 252 A (1999-04-01), None
Communication and Search Report dated Mar. 16, 2000 from European Patent Office regarding European Patent Application No. 99309300.
IEEE Transactions on Consumer Electronics, “Fast Settling PLL Frequency Synthesizer Utilizing the Frequency Detector Method Speedup Circuit”, Yasuaki Sumi, et al. Aug. 1998, vol. 43, No.3.

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