PLL response time accelerating system using a frequency detector

Details PLL response time accelerating system using a frequency detector PLL response time accelerating system using a frequency detector

1998-04-08

2000-05-09

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331 1A, 331 1Y, 331 17, 331 25, 331 27, H03L 7087, H03L 7089

Patent

active

060609532

ABSTRACT:
A PLL response time is accelerated with a frequency detector counter. The PLL utilizes both a phase frequency detector and the frequency detector counter. Initially, the operation of the PLL is controlled by the frequency detector counter and the output of phase frequency detector does not affect the PLL system. During this period, the PLL synchronizes to an input clock frequency. After the PLL reaches a predetermined frequency range, the frequency detector counter stops working. Thereafter, the phase frequency detector controls the operation of the PLL. During this period, the PLL synchronizes to both the frequency and the phase of the input signal.

REFERENCES:
patent: 4069462 (1978-01-01), Dunn
patent: 4547747 (1985-10-01), Wolaver et al.
patent: 4987355 (1991-01-01), Leaper et al.
patent: 5446416 (1995-08-01), Lin et al.

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