PLL (Phase-Locked Loop) circuit

Details PLL (Phase-Locked Loop) circuit PLL (Phase-Locked Loop) circuit

Filed on

2006-05-23

Date issued

2006-05-23

Examiner

Chin, Stephen (Department: 2631)

Patent Class

Pulse or digital communications

SubClass

Synchronizers

SubSubClass

Synchronizing the sampling time of digital data

Other Related Categories

C375S226000

Type

Reexamination Certificate

Status

active

Patent number

07050520

Description

ABSTRACT:
If a phase difference between a synchronizing source signal F1and a comparison signal F2is higher than a first lower limit a or lower than a first upper limit b, a comparator3selects this phase difference, if the phase difference is not higher than the lower limit a, selects the lower limit a, and if the phase difference is not lower than the upper limit b, selects the upper limit b, and a divider7A outputs a comparison signal F2obtained by dividing a frequency of an output signal F0, to change a phase of the signal F2so that if the phase difference is not higher than a second lower limit e lower than the lower limit a, the phase difference may become the lower limit a and, if the phase difference is higher than a second upper limit f higher than the upper limit b, the phase difference may become the upper limit b.

REFERENCES:
patent: 6188740 (2001-02-01), Tomaru
patent: 2002/0163391 (2002-11-01), Peterzell
patent: 2-180429 (1990-07-01), None
patent: 2000-68824 (2000-03-01), None

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