PLL output clock stabilization circuit

Details PLL output clock stabilization circuit PLL output clock stabilization circuit

2007-07-31

2007-07-31

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S147000

Reexamination Certificate

active

11153487

ABSTRACT:
A circuit includes: a PLL circuit which multiplies a reference clock by a multiplication factor and outputs a PLL clock; a first counter which counts up with the PLL clock for a fixed period of time; a comparator which compares a count value of the first counter with the multiplication factor; a second counter which counts up the number of times the comparison values have been matched for the fixed period of time; and an output unit which generates an enable signal when a count value of the second counter reaches the number of times the circuit waits for stability, and opens a gate to transmit the PLL clock in response to the enable signal.

REFERENCES:
patent: 6624681 (2003-09-01), Loyer et al.
patent: 6782486 (2004-08-01), Miranda et al.
patent: 2002/0087904 (2002-07-01), Cai
patent: 2004/0000939 (2004-01-01), Meguro
patent: 11-069263 (1999-03-01), None
Motrola Users Manual “On-chip Clock Synthesis (OCCS)”, published in Jan. 2001, specifically Figure 6-3 on p. 6-7 and section 6.8.1.3, “PLL Frequency Lock Detector”, on p. 6-9 in the manual.

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