PLL lock detection using a cycle slip detector with clock...

Details PLL lock detection using a cycle slip detector with clock... PLL lock detection using a cycle slip detector with clock...

2001-12-10

2002-10-15

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By frequency

C327S156000, C327S163000

Reexamination Certificate

active

06466058

ABSTRACT:

TECHNICAL FIELD OF INVENTION
The present invention relates generally to the field of phase locked loops, and more specifically to a lock detection circuit using a cycle slip detector with clock presence detection, permitting a large variation of the clock phase or frequency and adequate time for the PLL to react to the disturbance without causing false alarms, while providing an alarm to PLL behavior consistent with a significant deviation from the lock condition in a small, low power and low noise digital solution.
BACKGROUND OF THE INVENTION
The phase lock loop (PLL) is commonly used in digital circuitry to provide precise phase and frequency locking and synchronization of clock signals. Applications include, for example, anything requiring clock synchronization or clock synthesis, such as data transmission and telecommunications.
FIG. 1
illustrates a typical PLL circuit of a prior art. The PLL
100
of
FIG. 1
includes a phase/frequency detector
110
, a charge pump
120
, a loop filter
130
, a voltage controlled oscillator (VCO) a buffer inverter
150
for the VCO output PLL_OUT, and a frequency divider
160
. The phase/frequency detector
110
compares the phase and frequency of an input reference clock signal REF_CLK with those of a feedback signal FB_VCO and in response generates phase/frequency correction signals for the charge pump
120
. The phase/frequency correction signals comprise an Up signal and a Down signal transmitted on two separate signal paths. The Up and Down signals depend upon the relationship of the phase of the feedback signal FB_VCO to the input clock signal REF_CLK. For example, when the input clock signal REF_CLK and the feedback signal FB_VCO are in a perfect phase lock, the Up and Down signals generated by the phase/frequency detector
110
have perfectly matched pulses with an equal pulse width, as shown in FIG.
2
A.
FIG. 2B
shows the pulses of the up and down signals when an up shifting of the phase locked loop output signal PLL_OUT is required to enable the feedback signal FB_VCO to be phase locked with the input clock signal REF_CLK. In this case, the pulse width of the up signal is greater than that of the down signal. Only the leading edges of the corresponding pulses of the up an down signal are timed to coincide with each other, whereas the trailing edges of the up signal pulses lag behind those of the corresponding down signals pulses and vary with the timing difference between the clocks input to the phase/frequency detector
110
.
FIG. 2C
shows the pulses of the up and down signals when a downshifting of the phase locked loop output signal PLL_OUT is required to enable the feedback signal FB_VCO to be phase locked with the input clock signal REF_CLK. In this situation, the pulse width of the down signal is greater than that of the up signal. Here, only the trailing edges of the corresponding pulses of the up an down signal are timed to coincide with each other, whereas the leading edges of the down signal pulses lead ahead those of the corresponding up signals pulses and vary with the timing difference between the clocks input to the phase/frequency detector
110
.
Referring back to
FIG. 1
, the charge pump
120
generates a pump current I
C
in response to receiving the up and down signals from the phase/frequency detector
110
. The charge pump
120
detects a difference between the pulse width of the up and down signals generated by the phase/frequency detector
110
and adjusts the pump current I
C
if the pulses of the up and down signals do not match each other. For example, when the input clock signal REF_CLK and feedback signal FB_VCO are in a perfect phase lock and the up and down signal pulses are perfectly matched as shown in
FIG. 2A
, no phase or frequency shift in the output signal PLL_OUT is required, and therefore no change in the pump current I
C
is required.
In the case in which the phase/frequency detector
110
outputs up and down signal pulses as shown in
FIG. 2B
, the charge pump
120
determines that the pulse width of the up signal is greater than that of the down signal and in response adjusts the pump current I
C
upward to increase the frequency F
HI
of the output signal PLL_OUT, such that the frequency of the feedback signal FB_VCO is increased to achieve a phase lock with the input clock signal REF_CLK. In the case in which the phase/frequency detector
110
outputs up and down signal pulses as shown in
FIG. 2C
, the charge pump
120
determines that the pulse width of the down signal is greater than that of the up signal and in response adjust the pump current I
C
downward to decrease the frequency of the output signal PLL_OUT in order to achieve a phase lock between the signals REF_CLK and FB_VCO.
In this way, the conventional PLL is able to react to a limited phase difference between the input reference clock and the feedback VCO clock in order to regain frequency lock. Generally, for example, this allowable phase difference is less than 360 degrees.
The loop filter
130
in
FIG. 1
may be either a conventional passive loop filter or a conventional active loop filter which filters out undesirable noises and high frequency jitters in the pump current signal I
C
generated by the charge pump
120
.
The loop filter
130
outputs a control voltage V
C
to the VCO
140
, which in response generates a phase locked loop output signal PLL_OUT having a typically high output frequency F
HI
. The output frequency F
HI
generated by the VCO
140
is dependent upon the control voltage V
C
. In a PLL feedback loop, the conventional PLL
100
may include a frequency divider
160
which divides the output frequency F
HI
of the PLL by a predetermined divisor M, to generate the feedback signal FB_VCO, which is typically divided down to a lower frequency F
LO
. The divisor M, that is, the ratio of the frequency F
HI
of the PLL output signal PLL_OUT to the frequency F
LO
of the feedback signal FB_VCO, is determined by the desired frequency F
HI
of the output signal PLL_OUT relative to the frequency of the input clock signal REF_CLK.
When the input clock signal REF_CLK is initially provided to the phase/frequency detector
110
in the conventional PLL as shown in
FIG. 1
, the control voltage V
C
from the loop filter
130
may take a finite time before it settles to a steady-state voltage level to achieve a phase lock.
FIG. 3
illustrates a typical curve of the loop filter control voltage vs. time (V
C
vs. t)
180
, which shows the magnitude of the loop filter control voltage V
C
from the time of starting the input clock signal REF_CLK at V
CI
(initial control voltage) to the time of achieving a steady-state voltage V
CF
(final control voltage) at point C. Prior to the steady-state point C, the loop filter control voltage V
C
, which controls the frequency F
HI
of the PLL output signal PLL_OUT, may overshoot A and undershoot B again due to relatively large variations in the up and down signals from the phase/frequency detector
110
shortly after the phase locking operation is initiated. In addition, the initial control voltage V
CI
corresponds to an initial VCO starting frequency which may be very low. Therefore, the time required t
LOCK
, for the PLL to achieve lock after the REF_CLK signal is initially applied, may involve a substantial delay.
Additionally, during a transient state prior to achieving the steady state frequency, the control voltage V
C
may cause the conventional PLL as shown in
FIG. 1
to achieve a “false phase lock” condition as V
C
crosses the final control voltage set point V
CF
, yet is still in a transient state until the voltage level of V
C
stabilizes in correspondence with the feedback.
In order to avoid data errors which may occur due to a false lock from a PLL, prior art using fixed time delays have been provided after the clock start. However, a fixed time delay does not ensure a true phase lock because the duration of the transient state prior to achieving the steady state will not be the same for each phase locking operation because of the nonlinear nature of loc

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