PLL lock detection circuit using edge detection and a state...

Details PLL lock detection circuit using edge detection and a state... PLL lock detection circuit using edge detection and a state...

2006-08-01

2006-08-01

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

07084681

ABSTRACT:
A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit uses a state machine to assert a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, the lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

REFERENCES:
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patent: 5394444 (1995-02-01), Silvey et al.
patent: 5790613 (1998-08-01), Tateishi
patent: 6115438 (2000-09-01), Andresen
patent: 6441691 (2002-08-01), Jones et al.
patent: 6466058 (2002-10-01), Goldman
patent: 6794944 (2004-09-01), Hirai
patent: 2002/0180540 (2002-12-01), Hirai

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