PLL jitter measuring method and integrated circuit therewith

Details PLL jitter measuring method and integrated circuit therewith PLL jitter measuring method and integrated circuit therewith

1998-03-25

2001-02-06

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Electrical signal parameter measurement system

C324S622000

Reexamination Certificate

active

06185510

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit having a PLL that generates an internal clock signal and to a PLL jitter measuring method thereof.
2. Description of the Related Art
In recent years, integrated circuits have been increasingly used for data transmission systems. As an example of data transmission systems, a so-called Rambus system that bidirectionally transmits data between a master device and a slave device is known.
In the Rambus system, data is transmitted from a master device to a slave device in synchronization with a transmission clock signal (that is referred to as cfm (clock from master) signal). The slave device receives the transmission data from the master device in synchronization with the transmission clock cfm signal. On the other hand, data is transmitted from the slave device to the master device in synchronization with a transmission clock signal (that is referred to as ctm (clock to master) signal). The master device receives the transmission signal from the slave device in synchronization with the transmission clock ctm signal.
Each of the master device and the slave device used in the Rambus system should internally generate the transmission clock signal and the reception clock signal that synchronizes with the transmission clock signal. Thus, each of the master device and the slave device has a PLL that generates the transmission clock signal and another PLL that generates the reception clock signal and that is a phase locked loop which is asynchronized with the transmission clock signal of the master device or the slave device.
On the other hand, in the data transmission systems such as the Rambus system, the transmission clock signal and the reception clock signal should be prevented from being affected by clock skews due to jitters. In particular, when the frequencies of the transmission clock signal and the reception clock signals are high, the influences of the jitters to these clock signals should be monitored and prevented so that the relevant integrated circuit can be normally operated.
In the master device and the slave device used in the Rambus system, the jitter of the transmission clock signal generated by the PLL is indirectly measured by monitoring and testing the transmission data that is output from each device to the outside.
However, the jitter of the reception clock signal generated in each device is not output to the outside thereof. Thus, this jitter cannot be measured from the outside of the device.
Consequently, as a conventional jitter measuring method, the package of the integrated circuit of each device is removed. A measurement probe is directly contacted to the PLL that generates the reception clock signal. The output signal of the PLL is observed with an oscilloscope so as to measure the jitter of the reception clock signal.
However, in the conventional method, to measure the jitter of the PLL that generates the reception clock signal, the package of the integrated circuit should be removed. Thus, it is impossible to measure jitters of all integrated circuits to be tested.
On the other hand, in Japanese Patent Laid-Open Publication No. 8-62298, a semiconductor integrated circuit testing method is disclosed. In this method, data that is input to a high speed interface portion is looped as output data back to the high speed interface portion. The output data is tested by an LSI tester.
However, this related art reference teaches only the loopback of input data to the outside. However, it teaches neither a reception clock signal generated in an integrated circuit, nor the measurement of a jitter of a reception clock signal.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a PLL jitter measuring method that allows a jitter of an internal clock signal generated by a PLL and that is not output to the outside of an integrated circuit to be measured without need to remove the package of the integrated circuit.
Another object of the present invention is to provide a PLL jitter measuring method suitable for an integrated circuit that structures a master device or a slave device of the Rambus system.
A further object of the present invention is to provide an integrated circuit that outputs a signal containing a jitter component of an internal clock signal generated therein and that allows a jitter of the internal clock signal to be measured from the outside of the integrated circuit.
A more further object of the present invention is to provide an integrated circuit that allows a jitter of an external clock signal or a transmission clock signal that is output to the outside to be measured.
A first aspect of the present invention is a PLL jitter measuring method used for an integrated circuit with a PLL that generates an internal clock signal, comprising the steps of extracting jitter information of the internal clock signal of the PLL as an output signal to the outside of the integrated circuit without removing a package of the integrated circuit, and measuring the jitter of the internal clock signal with the extracted output signal. The integrated circuit has a PLL measurement functional circuit for outputting the jitter fs information to the outside along with the PLL that generates the internal clock signal. The output signal is sent to an IC tester or the like through the PLL measurement function circuit.
A second aspect of the present invention is an integrated circuit, comprising a PLL for generating an internal clock signal, and a PLL measurement functional circuit having a function for measuring a jitter of the internal clock signal of the PLL, wherein the PLL measurement functional circuit has a sending means for receiving an input signal for measuring the jitter of the internal clock frequency of the PLL, sampling the input signal with the internal clock signal, and sending the sampled signal as an output signal to the outside of the integrated circuit. Thus, an integrated circuit that allows a jitter of an internal clock signal to be measured without need to remove the package thereof can be obtained. These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings.


REFERENCES:
patent: 5295079 (1994-03-01), Wong et al.
patent: 5381085 (1995-01-01), Fischer
patent: 5485490 (1996-01-01), Leung et al.
patent: 5889435 (1999-03-01), Smith et al.
patent: 61-151483 (1986-07-01), None
patent: 62-11181 (1987-01-01), None
patent: 8-62298 (1996-03-01), None

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