Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Patent
1983-07-22
1986-02-25
LaRoche, Eugene R.
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
331 14, 331 17, 331 25, H03L 706
Patent
active
045730245
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a method of bringing an oscillator into phase with an incoming signal, together with an apparatus for carrying out the method.
BACKGROUND ART
For bringing an oscillator into phase with an incoming signal it is known to use a so-called phase-locked loop (PLL) which employs analog signal processing. However, such loops are not suitable for interaction with circuits operating digitally and implemented as integrated circuits.
DISCLOSURE OF INVENTION
An object of the present invention is therefore to provide a method for digitally bringing an oscillator into phase with an incoming signal and also to provide an apparatus for carrying out the method, such apparatus being realizable with integrated circuits.
The object is achieved by the method and apparatus in accordance with the invention having been given the characterizing features disclosed in the claims.
BRIEF DESCRIPTION OF DRAWINGS
The invention is described more closely below with reference to the appended drawing, in which FIG. 1 illustrates an embodiment of the apparatus in accordance with the invention for bringing an oscillator into phase with an incoming signal, FIG. 2 illustrates the sampling of the incoming signal when the oscillator is brought into phase therewith, FIG. 3 illustrates the sampling of the incoming signal when the oscillator is out of phase therewith, FIG. 4 illustrates the frequency of the oscillator signal as a function of time when the oscillator is in phase with the incoming signal, and FIG. 5 illustrates the resulting jitter in the oscillator output signal.
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 illustrates an embodiment of an apparatus in accordance with the invention for bringing an oscillator 1 into phase with an incoming signal, and in the illustrated embodiment this signal is assumed to be a biphase-modulated data signal, of which three successive data bits having the same value are shown in FIG. 2. The biphase-modulated data signal is applied to the input 2 of a sampling circuit 3, which is controlled by the output signal of the oscillator 1 at the output 1a. In the embodiment illustrated it is intended to sample the incoming, biphase-modulated data signal four times per bit period T. When the oscillator output signal is in phase with the incoming signal, the samples will be distributed in the manner shown in FIG. 2, where the four samples within the illustrated bit periods are denoted respectively A', B', C', D'; A", B"; C", D" and A'", B'", C'", D'". In accordance with the invention, the samples are fed to a comparator 4 which is adapted to emit, in response to whether the sample polarity is positive or negative, sequential high or low level signals, i.e. binary ones or zeroes. Accordingly, a series of binary ones and zeroes will occur at the output of the comparator 4, where a one signifies that the corresponding sample was positive, while a zero signifies that the corresponding sample was negative or vice versa. These ones and zeroes are then applied in order to a shift register 5 having three stages I, II and III in the illustrated embodiment. The shift register outputs are connected to a logic circuit 6 which, on the basis of the contents of the shift register 5, is adapted to determine whether the phase difference between the output signal of the oscillator 1 and the incoming signal to the input 2 is positive or negative, and in response thereto to emit a high or low level signal, i.e. a binary one or zero. In accordance with the invention the oscillator 1 is adapted to emit an output signal at its output 1a, which assumes one of two frequencies in response to the output signal from the logic circuit 6. The frequencies of the oscillator output signal are, in accordance with the invention, so selected that one frequency is predeterminately higher, while the second frequency is predeterminately lower than four times the frequency of the incoming signal at the input 2 according to the example. The oscillator 1 is thus controlled binarily from the lo
REFERENCES:
patent: 4179671 (1979-12-01), Yoshida et al.
patent: 4330759 (1982-05-01), Anderson
patent: 4333060 (1982-06-01), Mosley, Jr. et al.
patent: 4422176 (1983-12-01), Summers
patent: 4513255 (1985-04-01), Terbrack
LaRoche Eugene R.
Mis D. C.
Telefonaktiebolaget L M Ericsson
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