PLL frequency synthesizer with K multiplication in addition to d

Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation

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331 1A, 331 18, 331 57, 331 25, 327116, 327119, 327107, 327159, H03L 708, H03L 7099, H03L 718, H03B 1900

Patent

active

059458810

ABSTRACT:
A frequency synthesizer is supplied with an input signal of frequency .function..sub.i to provide an output signal .function..sub.o where .function..sub.o=.function..sub.i M/N and M and N are integers. The input signal is first applied to a divider circuit for division by M/K where K is an integer and the resultant is applied as inputs to a phase locked loop. The phase locked loop includes a ring oscillator of frequency .function..sub.i N/M, a frequency multiplier circuit for multiplying by K, and a frequency divider circuit for dividing by N. The ring oscillator uses a combinational logic circuit that combines the outputs of four differential delay elements to produce a frequency multiplication of four.

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patent: 5530387 (1996-06-01), Kim
patent: 5548251 (1996-08-01), Chou et al.
patent: 5565817 (1996-10-01), Lakshmikumar
patent: 5786715 (1998-07-01), Halepete

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