PLL frequency synthesizer having a power saving circuit

Details PLL frequency synthesizer having a power saving circuit PLL frequency synthesizer having a power saving circuit

1991-10-17

1993-01-19

Pascal, Robert J.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331 25, 331186, H03L 700

Patent

active

051809923

ABSTRACT:
A PLL frequency synthesizer includes a reset circuit which determines whether or not an oscillator starts to normally generate an oscillation signal in response to a power save signal which intermittently operates the oscillator in a standby mode and which outputs a reset signal to a prescaler when it is determined that the oscillator normally generates the oscillation signal. A hold circuit prevents a frequency-divided signal being output from the prescaler to a programmable counter and an initial phase detection circuit until the prescaler is reset to an initial state in response to the reset signal and starts to normally generate the frequency-divided signal.

REFERENCES:
patent: 4631496 (1986-12-01), Borras et al.

Affiliated with

Also associated with

Rating

PLL frequency synthesizer having a power saving circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with PLL frequency synthesizer having a power saving circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PLL frequency synthesizer having a power saving circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-104144