PLL frequency synthesizer circuit

Details PLL frequency synthesizer circuit PLL frequency synthesizer circuit

2001-03-16

2003-02-11

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331SDIG002

Reexamination Certificate

active

06518845

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a frequency synthesizer circuit employing a local oscillating circuit and a PLL (Phase Locked Loop), and, in particular, a PLL frequency synthesizer circuit in which a locking-up time at a time of lock frequency switching is shortened.
2. Description of the Related Art
FIGS. 1
,
2
and
3
illustrate such a PLL frequency synthesizer circuit in the related art.
FIG. 1
is a block diagram showing a PLL frequency synthesizer circuit in the related art.
FIG. 2
is a timing chart of an operation of the PLL frequency synthesizer circuit shown in FIG.
1
.
FIG. 3
illustrates a locking-up operation of the PLL frequency synthesizer circuit shown in FIG.
1
.
As shown in the figures, the PLL frequency synthesizer circuit in the related art includes a phase comparator
1
which calculates a phase difference between a reference frequency fr output after undergoing frequency dividing from a reference frequency divider
6
and a comparing frequency fp output after undergoing frequency dividing from a comparing frequency divider
7
, and outputs phase-difference signals PP and PR based on the thus-calculated phase difference, a charge pump
2
which outputs an output current Do specified based on the phase-difference signals PP and PR, a low-pass filter
3
generates a direct-current control voltage Vc based on this output current Do, and removes unnecessary frequency components included in the output current Do, a voltage-controlled oscillator (VCO)
4
which generates a oscillated frequency fvco based on the direct-current control voltage Vc, and a pre-scaler
5
which renders frequency dividing on the oscillated frequency fvco into a predetermined frequency fpin and outputs the-thus-obtained frequency-divided frequency fpin to the comparing frequency divider
7
.
The reference frequency divider
6
generates the reference frequency fr based on a reference clock signal fc generated by a quarz-crystal oscillating circuit
61
based on an externally input instruction signal OSCin, and a frequency-dividing value signal and a counter-setting signal STBR generated by a shift register
71
. The comparing frequency divider
7
generates the comparison frequency fp from the frequency-divided frequency fpin output from the pre-scaler
5
and the frequency-dividing value signal and counter-setting signal STBP output from the shift register
71
. The shift register
71
has a clock signal CLOCK, a data signal DATA and a control signal LE input externally thereto, generates the frequency-dividing value signal from the clock signal CLOCK and data signal DATA, and, also, based on the control signal LE, generates the counter-setting signals STBR and STBP which control taking in and storing of the frequency-dividing value signal by the reference frequency divider
6
or comparing frequency divider
7
.
The locking-up operation at the time of lock-frequency switching of the PLL frequency synthesizer circuit having the above-described configuration will now be described. First, at the time of T
1
(FIG.
2
), both the reference frequency fr of the reference frequency divider
6
and the comparison frequency fp of the comparing frequency divider
7
are locked to one another at a coincident lock frequency fvco
1
, and the phase-difference signals PP and PR output from the phase comparator
1
do not have pulse widths indicating a phase difference. When no phase difference is detected by the phase comparator
1
, the phase-difference signals output are merely of impulses (shown in
FIG. 2
as vertical lines) and do not have pulses having pulse widths indicating a phase difference.
When the counter-setting signal STBP for changing the frequency-dividing value is output to the comparing frequency divider
7
from the shift register
71
in order that the lock frequency is to be changed (channel switching) from fvco
1
into fvco
2
(fvco
1
<fvco
2
) at the time T
2
in the above-mentioned locked condition, the locking-up operation is started. The locking-up operation is an operation in that the phase comparator
1
compares the reference frequency fr with the comparison frequency fp after the counter-setting signal STBP is input, the phase difference corresponding to the delay of the comparison frequency fp is calculated, and the phase-difference signals PP and PR are output based on the thus-obtained phase difference.
In the beginning of the locking-up operation immediately after the change from the lock frequency fvco
1
, the phase-difference signal PP having the increasing frequency is output with the pulse width corresponding to the above-mentioned phase difference. This phase-difference signal PP is input to the charge pump
2
, and the charge pump
2
outputs the output current Do for the time corresponding to the above-mentioned phase-different signal PP. This output current Do is converted into the direct-current control voltage Vc by the low-pass filter
3
, and, based on this direct-current control voltage Vc, the VCO
4
converts this voltage value into a frequency, and outputs the oscillated frequency fvco of an internal change signal. As shown in
FIG. 3
, this oscillated frequency fvco undergoes feedback control by a PLL circuit of a closed loop including the phase comparator
1
, charge pump
2
, low-pass filter
3
, voltage-controlled oscillator
4
, pre-scalar and comparing frequency divider
7
so that the frequency is increased from the original lock frequency fvco
1
.
When the above-mentioned oscillated frequency fvco is increased so that the phase between the reference frequency fr and comparison frequency fp is inverted at the time T
30
(first phase inversion), the phase comparator
1
outputs the phase-difference signal PR for decreasing the frequency with the pulse width corresponding to the phase difference obtained through the calculation. This phase-difference signal PR is input to the charge pump
2
, and the charge pump
2
outputs the output current Do for the time corresponding to the phase-difference signal PR. This output current Do is converted into the direct-current control voltage Vc by the low-pass filter
3
, and, based on the direct-current control voltage Vc, the VCO
5
outputs the oscillated frequency fvco.
This oscillated frequency fvco is controlled by the above-mentioned PLL circuit so that the frequency is decreased, as shown in FIG.
3
. When the oscillated frequency fvco is thus decreased, and the phase is again inverted (second phase inversion) at the time T
40
, the above-mentioned operation is repeated, and, thereby, the frequency fvco changes so that the amplitude of overshooting becomes smaller and the frequency converges into the lock frequency fvco
2
, the target frequency of the channel switching.
Because the PLL frequency synthesizer circuit in the related art is configured as described above, the overshooting occurs when the vibration condition is repeated and the frequency converges into the target lock frequency since the counter-setting signal STBP for the channel switching is output to the comparing frequency divider
7
, and, thereby, shifting into the target lock frequency cannot be rendered smoothly, and, thus, the locking-up time is long.
PLL frequency synthesizer circuits are disclosed in Japanese Laid-Open Patent Applications Nos. 2-113726, 4-297128, 8-307254 and 9-214338.
The PLL frequency synthesizer circuit disclosed in Japanese Laid-Open Patent Application No. 2-113726 renders shortening of the locking-up time by controlling the output current of the charge pump by changing connection of a plurality of external resistors. However, the S/N ratio (ratio of signal to noise) is degraded and also the C/N ratio (ratio of carrier to noise) is degraded when the capability of the charge pump is increased. Thereby, the characteristics (for exmaple, PLL loop gain) differs between the steady locked condition and locking-up condition, and, as a result, a relocking phenomena may occur.
The PLL frequency synthesizer circuit disclosed in Japanese Laid-Open Paten

Affiliated with

Also associated with

Rating

PLL frequency synthesizer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with PLL frequency synthesizer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PLL frequency synthesizer circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3147156