Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
1998-12-30
2001-01-16
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S025000, C331S014000, C327S105000, C327S156000, C455S266000, C455S260000
Reexamination Certificate
active
06175281
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a PLL frequency synthesizer used for a portable terminal or the like.
BACKGROUND ART
An example of a conventional PLL frequency synthesizer will be described in conjunction with FIG.
10
.
FIG. 10
is a block diagram showing the conventional PLL frequency synthesizer.
Referring to
FIG. 10
, reference numeral
1
denotes a reference frequency generator issuing a reference frequency signal.
Reference numeral
2
denotes a phase lock loop circuit (hereinafter referred to as “FLL circuit”) which is connected to the reference frequency generator
1
to divide the reference frequency issued from the reference frequency generator
1
by N so as to provide a first frequency.
The PLL circuit
2
divides the output frequency received from a first VCO circuit
4
by M to provide a second frequency.
The PLL circuit
2
compares the phase of the first frequency obtained by dividing the output frequency by M with that of the second frequency obtained by dividing the reference frequency by N and outputs a phase error signal regarding the phase error of the first frequency and the second frequency.
Reference numeral
3
denotes a first loop filter (hereinafter referred to as “LOOP_FL”) which is connected to the PLL circuit
2
and smoothes the phase error signal issued from the PLL circuit
2
.
Reference numeral
4
denotes a first voltage controlled oscillator (hereinafter referred to as “VCO”) circuit which is connected to a first LOOP_FL
3
and outputs a signal of the output frequency based on the phase error signal which has been smoothed by the first LOOP_FL
3
.
The signals of the frequencies to be controlled by the conventional PLL frequency synthesizer are controlled by relational expression (1) given below.
And the conventional PLL frequency synthesizer outputs a plurality of types of frequency signals within a predetermined range that satisfies the following relational expression (1):
F
0
=(
M/N
)×
FS
(1)
where F
0
indicates output frequency, FS indicates reference frequency, M indicates the dividing number of output frequency, and N indicates the dividing number of reference frequency.
The mobile radio systems are shifting from analog systems to digital systems.
Some mobile radio systems are beginning to call for mobile terminals compatible with both analog systems and digital systems.
In general, the PLL frequency synthesizer in an analog system mobile terminal is required to have a higher signal-to-noise power ratio (hereinafter referred to as “S/N ratio”) and a higher carrier-to-noise (hereinafter referred to as “C/N ratio”) than those of a digital system PLL frequency synthesizer.
On the other hand, the PLL frequency synthesizer in a digital system mobile terminal is not required to provide such a high S/N ratio and C/N ratio as in the case of the PLL frequency synthesizer in the analog system mobile terminal, but it is required to have a quicker lockup time and a faster power rise than those in the analog system PLL frequency synthesizer.
The higher S/N ratio and C/N ratio conflict with the quicker lockup time and the faster power rise.
The PLL frequency synthesizer provided in the mobile terminal compatible with both analog system and digital system is required to provide a quicker lockup time and a faster power rise in a digital mode in which the digital system is used.
The PLL frequency synthesizer provided in the mobile terminal compatible with both analog system and digital system is also required to provide high S/N ratio and C/N ratio in an analog mode in which the analog system is used.
Hereinafter, the mobile terminal compatible with both digital system and analog system will be referred to as a “dual mode unit.”
Most conventional mobile terminals are compatible with only one type of system.
Even when a mobile terminal compatible with both analog system and digital system is available, the mobile terminal is provided with a PLL frequency synthesizer required for an analog system and a PLL frequency synthesizer required for a digital system.
In other words, the conventional mobile terminal compatible with both analog system and digital system has been constructed by many components, making it extremely difficult to reduce the size of the mobile terminal. Furthermore, since the conventional mobile terminal is composed of many components, the manufacturing cost of the mobile terminal has been extremely high.
The present invention has been made with a view toward solving the problems, and it is an object of the invention to achieve a simpler constitution of a PLL frequency synthesizer of a mobile terminal compatible with a plurality of systems by sharing a part of the PLL frequency synthesizer of the mobile terminal compatible with a plurality of systems among the plurality of systems and to provide a PLL frequency synthesizer that permits lower manufacturing cost thereof.
DISCLOSURE OF THE INVENTION
According to the present invention, there is provided a PLL frequency synthesizer having: a reference frequency generator which issues a first frequency signal; a PLL section which is connected to the reference frequency generator, receives the first frequency signal and a second frequency signal, and outputs a phase error signal based on the first frequency signal and the second frequency signal; a first filter which is connected to the PLL section, smoothes the phase error signal output from the PLL section according to a first reference, and outputs a first smoothed phase error signal; a second filter which is connected to the PLL section, smoothes the phase error signal output from the PLL section according to a second reference, and outputs a second smoothed phase error signal; a switch which is connected to the first filter and the second filter and issues, in a switching mode, the first smoothed phase error signal or the second smoothed phase error signal output from the first filter or the second filter; an output frequency generator which is connected to the switch and the PLL section and issues a second frequency signal based on the first smoothed phase error signal or the second smoothed phase error signal to the PLL section; and a switch controller which is connected to the switch to control the changeover of the switch.
Further according to the present invention, there is provided a PLL frequency synthesizer having: a reference frequency generator which issues a first frequency signal; a PLL section which is connected to the reference frequency generator, receives the first frequency signal and a second frequency signal, and outputs a phase error signal based on the first frequency signal and the second frequency signal; a first filter which smoothes the phase error signal according to a first reference and outputs a first smoothed phase error signal; a second filter which smoothes the phase error signal according to a second reference, and outputs a second smoothed phase error signal; a switch which is connected between the PLL section and the first filter and the second filter, and which issues, in a switching mode, the phase error signal issued from the PLL section; an output frequency generator which is connected to the first filter, the second filter, and the PLL section, and which issues a second frequency signal based on the first smoothed phase error signal or the second smoothed phase error signal to the PLL section; and a switch controller which is connected to the switch to control the changeover of the switch.
Further, in the PLL frequency synthesizer in accordance with the present invention, the output frequency generator has a first power supply and a second power supply, so that the first power supply is selected when the switch is changed over to the connection with the first filter by the switch controller, while the second power supply is selected when the switch is changed over to the connection with the second filter by the switch controller.
Further, in the PLL frequency synthesizer in accordance with the present invention, the first power supply defines the
Kinkead Arnold
Mitsubishi Denki & Kabushiki Kaisha
Rothwell Figg Ernst & Manbeck
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