PLL frequency synthesizer and method for controlling the PLL fre

Details PLL frequency synthesizer and method for controlling the PLL fre PLL frequency synthesizer and method for controlling the PLL fre

1999-02-08

2000-09-19

Kinkead, Arnold

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331176, 331179, 331 14, 327159, 375376, H03L 708, H03L 718

Patent

active

061218448

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a PLL frequency synthesizer, which is used in a cellular telephone or similar mobile telephone to switch frequencies at high speed, and a method for controlling the PLL frequency synthesizer.


TECHNICAL FIELD

FIG. 1 is a block diagram depicting the construction of an example of a conventional PLL frequency synthesizer disclosed, for example, in Japanese Patent Laid-Open Gazette No. 125270/94. In FIG. 1, reference numeral 1 denotes a reference oscillator which generates a reference frequency signal of a reference frequency; 2 denotes a frequency divider for dividing the frequency of the output from a voltage-controlled oscillator 6; 3 denotes a phase comparator which compares the phase of the reference frequency signal from the reference oscillator 1 and the phase of the frequency-divided signal from the frequency divider 2 and outputs a phase difference signal of a value corresponding to the detected phase difference; 4 denotes a charge pump which is driven by the phase difference signal from the phase comparator 3 and outputs a pulse signal of a width corresponding to the phase difference between the reference frequency signal and the frequency-divided signal; and 5 denotes a loop filter which smoothes the pulse signal from the charge pump 4 and applies it as a control signal to the voltage-controlled oscillator 6.
Next, the operation of the above prior art example will be described below.
The output signal from the voltage-controlled oscillator 6, which has a desired frequency, is frequency divided by the frequency divider 2 in accordance with the frequency dividing number set therein. When supplied with the reference frequency signal available from the reference oscillator 1 and the frequency-divided signal, the phase comparator 3 compares the phases of these signals and outputs, to the charge pump, a phase difference signal of a value corresponding to the phase difference. The charge pump 4 is driven by the phase difference signal from the phase comparator 3 and outputs, to the loop filter 5, a pulse signal of a width corresponding to the phase difference between the reference frequency signal and the frequency-divided signal. The loop filter 5 smoothes the pulse signal from the charge pump 4 and outputs a control voltage for controlling the voltage-controlled oscillator 6. When the loop filter 5 receives the pulse signal from the charge pump 4, a capacitor in the loop filter 5 is charged or charges stored in the capacitor are discharged. As the result of this, the control voltage varies which is applied to the voltage-controlled oscillator 6. Thus, when there is a phase difference between the reference frequency signal from the reference oscillator 1 and the frequency-divided signal from the frequency divider 2, the charge pump 4 outputs a pulse signal of a width corresponding to the phase difference; hence, the control voltage to be fed to the voltage-controlled oscillator 6 varies and the frequency of the output signal from the voltage-controlled oscillator 6 varies accordingly. This operation is continued until no phase difference is detected between the reference frequency signal and the frequency-divided signal. When the phase difference is no more detected, the PLL frequency synthesizer enters its frequency-locked state; the frequency of the output signal from the voltage-controlled oscillator 6 at this time becomes equal to a value of multiplication of the frequency of the reference frequency signal by the frequency dividing number set in the frequency divider 2. Accordingly, the output signal from the voltage-controlled oscillator 6 can be set at a frequency of an integral multiple of the reference frequency signal by changing the frequency dividing number (an integer) that is set in the frequency divider 2.
Since the conventional PLL frequency synthesizer has such a construction as described above, there is a problem that phase noise of the output signal from the voltage-controlled oscillator 6 and spurious components occurring near the desi

REFERENCES:
patent: 5334952 (1994-08-01), Maddy et al.

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