PLL frequency synthesizer

Details PLL frequency synthesizer PLL frequency synthesizer

1987-08-24

1989-01-10

LaRoche, Eugene R.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Search sweep of oscillator

331 17, 331 25, 331178, H03L 700

Patent

active

047976373

ABSTRACT:
A PLL frequency synthesizer comprises a voltage controlled oscillator which oscillates in response to a frequency signal corresponding to a control signal to be input and which outputs the frequency signal as an output of said PLL frequency synthesizer; a multiplier means for multiplying a reference frequency signal to be input; a mixer for mixing the frequency signal which is output from the voltage controlled oscillator and the multiplied reference frequency signal which is output from the multiplier, and for outputting a frequency signal representative of a difference therebetween; a variable frequency divider for dividing the difference frequency signal at a variable dividing ratio; a fixed frequency divider for dividing the reference frequency signal at a predetermined dividing ratio; a frequency phase comparator for detecting a phase difference between an output signal from the variable frequency divider and an output signal from the fixed frequency divider and for outputting a phase difference signal therebetween; a filter for removing high frequency components of the phase difference signal which is supplied as the control signal to the voltage controlled oscillator; and a device for switching the polarity of the phase difference signal. An output frequency of the voltage controlled oscillator can be switched to either a frequency higher than or a frequency lower than the frequency which is H (H is a positive integer) times as high as the output frequency of the multiplier, or the output frequency of the voltage controlled oscillator can be switched to either a frequency higher than the frequency which is H times as high as the output frequency of the multiplier or a frequency lower than the frequency which is (H+1) times as high as the output frequency of the multiplier.

REFERENCES:
patent: 4486717 (1984-12-01), Yamasaki

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