PLL frequency stabilization in data packet receivers

Telecommunications – Receiver or analog modulated signal frequency converter – Local control of receiver operation

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Details

370 941, 455265, 455308, 375 52, 375 83, H04B 110

Patent

active

049397907

ABSTRACT:
A frequency stabilization circuit for a PSK data packet receiver includes a reference oscillator for supplying a continuous reference signal to a limiter that supplies feeds received data packets to a phase locked loop detection circuit including a voltage controlled oscillator. The frequency of the continuous reference signal is close to the carrier frequency of the data packets and maintains the frequency of the voltage controlled oscillator close to the data packet carrier frequency between data packets. During data packets, the reference oscillator signal is "swamped out" by the limiter.

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