PLL/FLL circuit with gain control

Details PLL/FLL circuit with gain control PLL/FLL circuit with gain control

2011-02-08

2011-02-08

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S00100A, C331S00100A, C331S034000, C375S373000, C375S347000, C375S375000, C375S376000, C455S260000

Reexamination Certificate

active

07884676

ABSTRACT:
An FLL circuit having a capability of configuring a desired loop bandwidth in a short period of time is provided. An FDC17generates a feedback of an output signal of a VCO15. An error detector11detects an error of the output signal of the VCO15. A voltage retainer13retains an output of a control voltage of the VCO15. A reference signal generator16generates a reference signal. An adder14adds the reference signal to a control voltage outputted by the voltage retainer13. A Kv calculator18calculates a gain Kv of the VCO15based on a degree of transition of an output frequency of the VCO15. A loop bandwidth controller19adjusts, based on the gain Kv of the VCO15, a gain of a loop filter12to an optimum value, and configures a desired loop bandwidth.

REFERENCES:
patent: 7616067 (2009-11-01), Matsumoto et al.
patent: 2007-507985 (2007-03-01), None

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