PLL employing a sample-based capacitance multiplier

Details PLL employing a sample-based capacitance multiplier PLL employing a sample-based capacitance multiplier

2006-03-07

2006-03-07

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S025000, C331S1170FE, C331S167000, C331S17700V, C331S03600C

Reexamination Certificate

active

07009456

ABSTRACT:
A phase detector (PD) generates an up/down signal based on the phase error between data and clock signals input to the phase detector. A voltage controlled oscillator (VCO) generates the clock signal. The up/down signal is applied to a proportional charge pump and a truncated version of the up/down signal is applied to an integral charge pump. The proportional charge pump generates a first voltage for a first time period across a resistor based on the up/down signal, while the integral charge pump generates a second voltage for a second time period across a capacitor based upon the truncated version of the up/down signal and the sampling rate of the data signal by the PD. The second time period is less than the first time period. The first and second voltages are combined and applied to the VCO to drive the clock signal to synchronization with the data.

REFERENCES:
patent: 6614316 (2003-09-01), Masenas et al.
patent: 6693496 (2004-02-01), Lebouleux
patent: 6909329 (2005-06-01), Jasa et al.
Joseph Adler, “Clock-source jitter: A clear understanding aids oscillator selection”; EDN, Feb. 18, 1999, pp. 79-86.

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