Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2006-04-04
2006-04-04
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S160000, C327S117000, C377S047000
Reexamination Certificate
active
07023251
ABSTRACT:
An integrated circuit including a phase lock loop or delay lock loop) (PLL/DLL) circuit comprising: a clock input terminal for accepting a clock signal; a phase/frequency detector (PFD) circuit including a reference clock input connected to the clock input terminal and including a PFD feedback input and including a PFD output; a charge pump (CP) circuit; at least one external feedforward output terminal; a loop filter (LF); a loop controlled signal source (LCSS); and a feedback circuit connected between a LCSS output and the PFD feedback input, the feedback circuit including, an external feedback input terminal; first frequency selection circuitry to produce a first programmable feedback signal; second frequency selection circuitry to produce a second feedback signal; and multiplex circuitry connected with the LCSS output, the external feedback input terminal and the first and second frequency selection circuitry, to cause either the first programmable feedback signal or the second programmable feedback signal to be coupled to the PFD feedback input.
REFERENCES:
patent: 4633194 (1986-12-01), Kikuchi et al.
patent: 4862485 (1989-08-01), Guinea et al.
patent: 5036216 (1991-07-01), Hohmann et al.
patent: 5257294 (1993-10-01), Pinto et al.
patent: 5453706 (1995-09-01), Yee
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5744991 (1998-04-01), Jefferson et al.
patent: 5909126 (1999-06-01), Cliff et al.
patent: 6046603 (2000-04-01), New
patent: 6057704 (2000-05-01), New et al.
patent: 6091263 (2000-07-01), New et al.
patent: 6177844 (2001-01-01), Sung et al.
patent: 6181158 (2001-01-01), Cheung et al.
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6218876 (2001-04-01), Sung et al.
patent: 6252419 (2001-06-01), Sung et al.
patent: 6456132 (2002-08-01), Kouzuma
patent: 6633185 (2003-10-01), Starr
patent: 6812756 (2004-11-01), Starr
Altera, “Phase-Locked Loop (PLL) and LVDS Support in APEX 20KE Devices”, Marketing Bulletin # 276, Jan. 2000, 3 pp.
Hazavi, B. RF Microelectronics, “RF Synthesizer Architectures”, 1998, pp. 270-280.
MACOM, Programming Guide Integer N PLL Synthesizer 35 to 1100 MHZ, product information, 4 pp.
Mansukhani, A. “Phase Lock Loop Stability Analysis”, Applied Microwave & Wireless, 2000, pp. 30-38.
Perrott, M. H. et al., “A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation”, IEEE-J. of Solid State Circuits, vol. 32, No. 12, Dec. 1997, 13 pp.
Texas Instruments, “Low-Voltage 1.2 GHz Fractional-N/Integer-N Synthesizer”, TRF 2050, 34 pp.
XILINX, Virtex™-E 1.8 V, Field Programmable Gate Arrays, product description, Jul. 30, 2001, 7 pp.
XILINX, XC4000E and XC4000X Series Field Programmable Gate Arrays, product information, May 14, 1999, Version 1.6, 6-5 to 6-35.
Altera Corporation
Luu An T.
Wells Kenneth B.
LandOfFree
PLL/DLL circuitry programmable for high bandwidth and low... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with PLL/DLL circuitry programmable for high bandwidth and low..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PLL/DLL circuitry programmable for high bandwidth and low... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3623853