PLL device with plural phase comparators

Details PLL device with plural phase comparators PLL device with plural phase comparators

2002-02-05

2003-12-30

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331SDIG002, C331S017000, C331S00100A

Reexamination Certificate

active

06670855

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PLL device.
2. Background Art
An example of a PLL device of this type is shown for example in the drawing at page 32 of “SANYO TECHNICAL REVIEW” Vol. 10, No. 1, February 1978. This PLL device includes a reference oscillator generating a reference signal RF, a variable frequency divider dividing the frequency of an output signal FO to generate a feedback signal FV, and one phase comparator comparing the phase and frequency of the feedback signal FV with the phase and frequency of the reference signal FR to generate an error signal ER. Also provided are a low-pass filter generating a control voltage CV in response to the error signal ER, and a voltage-controlled oscillator generating the output signal FO in response to the control voltage CV.
However, this device has a disadvantage of having a long lock-up time (the time until synchronization with the output signal is reached), since it is a single-stage phase comparator type (the type using only one (single stage) phase comparator) and therefore, phase comparison is performed only once during one period of the reference signal.
Japanese Unexamined Patent Publication No. 10-135822 has been proposed to remove such disadvantage. According to this publication, there is provided a generating means for generating a plurality of reference signals having mutually differing phases, a plurality of (four, for example) frequency dividers dividing the frequency of the output signal of a voltage-controlled oscillator, a plurality of phase comparators comparing feedback signals from the frequency dividers with the reference signals, and a plurality of gates disposed at input sides of the frequency dividers.
However, the lock-up time is not shortened much even with the above configuration. The inventor of this application tried to track down the cause, and found it to be interference between outputs of the phase comparators when lock approached, which prevented smooth establishment of lock.
The inventor tried having the phase comparators deliver outputs initially, and then having one phase comparator deliver an output.
The inventor also tried out a configuration in which a value of a current of an error signal is switched at a certain timing during start-up.
However, it was found that the locking time A (
FIG. 1
) was not shortened much as shown in
FIG. 1
in either of the above-described configurations.
FIG. 1
shows a start-up characteristic in which the horizontal axis represents a time (elapsed time), and the vertical axis represents a frequency FO of an output signal.
The inventor tried to track down the cause, and found it to be that the time B at which the number of output stages of the phase comparators is switched is too early, and therefore, frequency fluctuation (lock failure) C arises.
Moreover, the device disclosed in the Japanese Unexamined Patent Publication No. 10-135822 has a disadvantage of having insufficient stability for a PLL loop, and low converging speed for the output signal.
The inventor tried to track down the cause, and found it to be that the principal parameters of the PLL loop (angular frequency, damping factor, cut-off frequency and so on) when one stage of the phase comparator and those when 4 stages of the phase comparators are used are the same.
Furthermore, the device disclosed in the Japanese Unexamined Patent Publication No. 10-135822 has a disadvantage of having large power consumption. The inventor tried to track down the cause, and found it to be the provision of frequency dividers.
If phase comparisons are performed four times during one period of the reference signal to further shorten the lock-up time, four frequency dividers are needed, and accordingly power consumption increases still more.
In addition, it has a third disadvantage that, because of use of a plurality of frequency dividers requiring a relatively large space, the device becomes large in size, the cost increases, and LSI implementation becomes difficult.
Accordingly, an object of the present invention in view of such conventional disadvantages is to provide a PLL device that has a short lock-up time, no interference between outputs of the phase comparators, no lock failure, and a small power consumption.
Another object of the present invention is to provide a PLL device that has a short lock-up time and no lock failure.
Still another object is of the present invention is to provide a PLL device that has a short lock-up time, superior stability and converging speed, and a small power consumption. Yet another object of the present invention is to provide a PLL device that has a short lock-up time and a small power consumption, and that is less expensive and easy to implement in an LSI.
DISCLOSURE OF THE INVENTION
A PLL device of a first aspect of the invention includes a generating means (
2
,
3
,
4
,
5
) for generating a plurality of reference signals having mutually differing phases, a plurality of variable frequency dividers (
11
,
12
,
13
,
14
) that divide a frequency of an output signal of a voltage-controlled oscillator (
15
) to generate feedback signals, a plurality of phase comparators (
7
,
8
,
9
,
10
) that compare phases between the reference signals and the feedback signals, and a control unit (
30
), wherein the control unit (
30
) allows, when deciding that a locked state has been reached in at least one of the phase comparators, this one of the phase comparators to keep on delivering an output thereof, and disables outputs of the other phase comparators.
A PLL device of a second aspect of the invention includes a generating means (
2
,
3
,
4
,
5
) for generating a plurality of reference signals having mutually differing phases, a plurality of variable frequency dividers (
11
,
12
,
13
,
14
) that divide a frequency of an output signal of a voltage-controlled oscillator (
15
) to generate feedback signals, a plurality of phase comparators (
7
,
8
,
9
,
10
) that compare phases between the reference signals and the feedback signals, and a control unit (
30
), wherein the control unit (
30
) allows, when deciding that at least one of the phase comparators is in a nearly locked state, one of the phase comparators to keep on delivering an output thereof, and disables outputs of the other phase comparators.
A PLL device of a third aspect of the invention includes a generating means (
2
,
3
,
4
,
5
) for generating a plurality of reference signals having mutually differing phases, a plurality of variable frequency dividers (
11
,
12
,
13
,
14
) that divide a frequency an output signal of a voltage-controlled oscillator (
15
) to generate feedback signals, a plurality of phase comparators (
7
,
8
,
9
,
10
) that compare phases between the reference signals and the feedback signals, and a control unit (
30
), wherein the control unit (
30
) allows one of the phase comparators to keep on delivering an output thereof, and disables outputs of the other phase comparators after a lapse of a predetermined time (S
14
) after a start signal or a frequency alteration command is input.
In the PLL device of the first, second or third aspect, it is permissible for the control unit (
30
) to have the variable frequency divider connected to the phase comparator that keeps on delivering its output continue to operate, and have the other variable frequency dividers stop their operations.
The PLL device of the first or second aspect may further include detectors (
37
,
38
,
39
,
40
) connected to the phase detectors for detecting the locked state or the nearly-locked state on the basis of the outputs of the phase comparators and outputting a detection signal to the control unit.
A PLL device of a fourth aspect of the invention includes a generating means (
2
,
3
,
4
,
5
) for generating a plurality of reference signals having mutually differing phases, a single divider or a plurality of variable frequency dividers (
11
,
12
,
13
,
14
) dividing a frequency of an output signal of a voltage-controlled oscillator (
15
) to

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