PLL device and programmable frequency-division device

Details PLL device and programmable frequency-division device PLL device and programmable frequency-division device

2001-06-22

2003-02-18

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S150000, C327S160000, C375S376000, C331SDIG002

Reexamination Certificate

active

06522183

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PLL device. The present invention also relates to a programmable frequency-division device.
2. Background Art
An example of a device of this type is shown on page 32 of the Sanyo Technical Review, Vol. 10, No. 1, February 1978. The device shown in
FIG. 1
therein includes a reference oscillator that generates a reference signal, a programmable divider that divides the frequency of the output signal to generate a feedback signal, and a single phase detector that compares the phase and frequency of the feedback signal FV with the phase and frequency of the reference signal and generates an error signal ER. Also provided are a low-pass filter that generates a control voltage corresponding to the error signal, and a voltage-controlled oscillator that generates the output signal corresponding to the control voltage.
If this PLL device is optimally designed, however, then in theory, there is a uniquely determined relationship between the frequency of the reference signal and the locking time. There is, accordingly, a disadvantage in that the locking time cannot be further shortened. To overcome this disadvantage, the present inventor has tried out configurations that generate a plurality of reference signals with different phases, and provide multiple phase-detector and programmable-divider stages. There is a disadvantage of high overall power consumption in these configurations, however, because power is consumed in the multiple phase-detector stages. Another disadvantage is that when there are multiple phase-detector and programmable-divider stages, the circuit becomes large in scale and difficult to implement in an LSI.
Moreover, because of the increasing number of subscribers in recent years, it has become impossible to provide the increased number of channels with existing frequency bands. A PLL device that can be used in high-frequency bands has therefore become necessary. Conventional programmable dividers, however, have the disadvantage of a limited maximum frequency value, due to the variability of their frequency-division ratios.
The fixed prescaler system has been devised to solve these problems. If a fixed divider with a frequency division ratio of four is provided in stages preceding and following the phase detector and programmable divider, for example, then the frequency of the reference signal becomes ¼ of the reference frequency. The number of phase comparisons then becomes ¼ of the original number, with the consequent disadvantage that the locking time is lengthened.
Other conventional PLL devices have been shown in Japanese Unexamined Patent Publications 10-190563 and 10-135822, but they also have the problems described above.
A programmable frequency-division device for use in a PLL device has been described in, for example, Japanese Unexamined Patent Publication 9-261048. This programmable frequency-division device includes a programmable divider that alternately divides the frequency of an output signal by N and N+1, a first output means, a second output means that delays the input signal by one-half period, and a selector circuit that selects the output of the second output means when the programmable divider divides by N, and selects the output of the first output means when the programmable divider divides by N+1; it outputs a signal with a frequency divided by N+½.
The programmable frequency-division device described above has the disadvantage of a poor jitter characteristic, however. That is, it does not output an accurate N+½ frequency division. When the present inventor identified the cause of this problem, it was found to be the insertion of an inverter between the input signal and the second output means. By inverting the input signal, this inverter causes a half-cycle delay with respect to the input signal in the second output means.
Because of the device characteristics of the inverter, the output of the second output means is delayed by more than one-half cycle, for which reason, it was found, frequency division by N+½ is not performed accurately.
The present invention addresses these types of past disadvantages, with the object of providing a PLL device that has a short locking time and low power consumption.
Another object of the invention is to provide a PLL device that can be used in high-frequency bands.
Still another object of the invention is to provide a PLL device that is low in cost and easy to implement in an LSI.
Yet another object of the invention is to provide a programmable frequency-division device with an improved jitter characteristic.
SUMMARY OF THE INVENTION
The foregoing and other objects are attained in accordance with a preferred embodiment of the invention by providing a PLL device comprising a voltage-controlled oscillator, a generating means that generates a plurality of reference signals with different phases, and a main divider that divides the frequency of the output signal of the voltage-controlled oscillator by a frequency-division ratio N
1
. An auxiliary divider divides the frequency of the output of the main divider by a frequency-division ratio N
2
. A distribution circuit distributes the output of the auxiliary divider as a plurality of feedback signals. Phase detectors compare the reference signals and the feedback signals, and generate error signals. Each of the main divider and the auxiliary divider has a programmable divider or a counter. The main divider and the auxiliary divider are both operative during start-up to shorten PLL lock-up time, and the auxiliary divider then powers down to reduce power consumption.
DISCLOSURE OF THE INVENTION
A PLL device according to one aspect of the invention comprises:
a programmable frequency-division device (
113
,
114
,
115
,
116
) that divides the frequency of the output of a voltage-controlled oscillator (
112
);
a reference signal generating means (
101
,
102
,
103
,
104
) generating a first reference signal and a second reference signal that differ in phase;
a first comparator (
106
) that compares the phases of said first reference signal and the output of said programmable frequency-division device;
a second comparator (
110
) that compares the phases of said second reference signal and the output of said programmable frequency-division device;
a detector (
118
,
120
,
122
,
124
) for detecting a locked state; and
a control unit (
117
);
wherein the control unit (
117
) causes both said first comparator (
106
) and said second comparator (
110
) to perform comparisons when the state is not locked, and causes one of said first comparator (
106
) and said second comparator (
110
) to perform comparisons when the state is locked.
A PLL device according to another aspect of the invention comprises:
a programmable frequency-division device (
113
,
114
,
115
,
116
) that divides the frequency of the output of a voltage-controlled oscillator (
112
);
a reference signal generating means (
101
,
102
,
103
,
104
) generating a first reference signal and a second reference signal that differ in phase;
a first comparator (
106
) that compares the phases of said first reference signal and the output of said programmable frequency-division device;
a second comparator (
110
) that compares the phases of said second reference signal and the output of said programmable frequency-division device; and
a control unit (
117
); wherein
when the control unit (
117
) alters the frequency-division ratio from a first value to a second value, it selects a predetermined one of said first comparator (
106
) and said second comparator (
110
) according to the difference between said first value and said second value, and causes that comparator to perform the comparison.
A PLL device according to another aspect of the invention comprises:
a reference signal generating means (
133
,
134
,
135
,
136
,
137
) generating a plurality of reference signals with different phases;
programmable dividers (
145
,
146
,
147
,
148
) receivi

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